Marvell Asia Pte., Ltd.

Cavium, Inc.

Marvell International Limited

Thucydides Xanthopoulos

Nitin Mohan

David Lin

Edward Wade Thoenes

David Albert Carlson

Scott E Meninger

Thomas Frederick Hummel

David Da-Wei Lin

Ethan Crain

Zahi S Abuhamdeh

Vasudevan Kandadi

Georgios Faldamis

Peter Rickenbach

Kandadi Vasudevan

Tyler Albarran

A system for performing a failure assessment of an IC may comprise a hardware subsystem and a control subsystem to control operations performed by the hardware subsystem. The hardware system may change a duration of cycles of a clocking signal on the IC, and stop the clocking signal at a selected clock cycle. The operations may comprise changing the duration of selected clock cycles across a block of clock cycles, and performing a binary search across the block of clock cycles, such that the selected clock cycles are temporally placed at selected different locations within the block of clock cycles. At each iteration of the binary search, the system determines when a failure occurs. When the binary search indicates a single clock cycle causing a failure, the system stops clocking transitions at the single clock cycle, and the system extracts data from one or more circuit components of the IC.

System and method for performing a failure assessment of an integrated circuit

A delay-locked loop (DLL) and corresponding method improve frequency of a chip. The DLL comprises a first programmable delay element configured to output a first clock, a second programmable delay element configured to output a second clock a phase detector. The phase detector includes a first clock input and a second clock input. The first and second programmable delay elements are further configured, in combination, to introduce a controllable skew between the first and second clocks. The DLL is configured to input the first and second clocks to the first and second clock inputs of the phase detector, respectively. The controllable skew is configured to improve the frequency of the chip.

DLL-based clocking architecture with programmable delay at phase detector inputs

In an embodiment, a method includes initializing an input clock rotating register by sending a reset signal synchronized to an input clock signal and initializing an output clock rotating register by sending the reset signal synchronized to an output clock signal. The method further providing a data input synchronized to the output clock to a plurality of mux-flops. The output clock rotating register activates one of the plurality of mux-flops to receive the data input. The method further includes forwarding the data input via the one of the plurality of mux-flops to a multiplexer. The multiplexer has a selection input of the input clock rotating register. The method further includes selecting the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock.

Traversing a variable delay line in a deterministic number of clock cycles

In an embodiment, a method includes filtering, with a low-pass filter, a voltage signal (V) of a chip to create a filtered signal (V). The method further includes dividing Vby a given factor. The method further includes determining whether a voltage droop occurred in Vby comparing Vto the divided V. The method further includes outputting a droop detection signal if Vis less than the divided V. In an embodiment, dividing Vby the given factor includes selecting, with a multiplexer, one of a plurality of divided Vsignals outputted by a voltage divider. The selecting is based on a selection signal.

Droop detection and mitigation

A circuit and corresponding method for dynamic voltage frequency scaling (DVFS) on a chip employ a delay-locked loop (DLL)-based clocking architecture. The circuit comprises a DLL including a fixed delay line path, with a first insertion delay, and variable delay line path, with a second insertion delay, and a clock generator. The clock generator is configured to source a DLL input clock to the fixed and variable delay line paths at a start-up frequency prior to a run-time frequency. The start-up frequency is lower relative to a target frequency for the chip. The run-time frequency is configured based on DVFS, following release of the chip from reset. The chip is configured to be released from reset with the DLL locked at the start-up frequency, enabling the second insertion delay to match the first insertion delay with the DLL locked at the start-up frequency.

Clocking architecture for DVFS with low-frequency DLL locking

A circuit and corresponding method enable glitch-free frequency. The circuit comprises a first delay circuit and a second delay circuit, configured to produce first and second propagated enables, respectively, from first and second input enables, respectively; and an output clock circuit. The output clock circuit is configured to produce an output clock that switches, glitch-free, between a first phase-locked clock and a second phase-locked. The first and second delay circuits are further configured to enable the output clock to be switched, glitch-free, by employing the second propagated enable to gate propagation of the first input enable and the first propagated enable to gate propagation of the second input enable, respectively. The first and second input enables are configured to be enabled, alternately, causing the output clock to switch between the first and second phase-locked clocks.

Glitch-free PLL Multiplexer

A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation, the data signal is oversampled based on the corresponding clock signal and multiple time-shifted versions of the corresponding clock signal. At least one signal of the corresponding clock signal and the multiple time-shifted versions of the corresponding clock signal is employed in sampling the data signal at a potential transition edge of the data signal.

Method and apparatus for aligning signals

An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that corresponds to a bit to be written to memory. The interface includes, for each line, circuitry for transmitting a bit to memory via the line, and a data de-skewer. For each line, the de-skewer receives a first data signal that represents a bit to be written. Each line has an inherent skew. The de-skewer generates a second data signal by applying a skew to the first. A selected extent of skew increases a likelihood of sampling the second data signal during a data-valid window thereof. The same de-skewer receives and skews a first data bit read from the memory.

Managing skew in data signals

According to at least one example embodiment, a semiconductor device is configured to gate power supply to a hardware component through a transistor coupled to the hardware component. The transistor is operated by a controller in a manner to limit electric current dissipated to the hardware component during a transition period. The controller is configured to gradually turn on, or off, the hardware component during a transition period by controlling at least one input signal to the transistor. Gradual turning on, or off, of the hardware component reduces electric current leakage through the hardware component and diminishes any potential disturbance to a ground reference coupled to the hardware component.

Method and apparatus for power gating hardware components in a chip device

A memory interface enables AC characterization under test conditions without requiring the use of Automated Test Equipment (ATE) and functional patterns. The memory controller may be configured to generate output patterns through the test interface and create a loopback path for input specification testing using an external stressed-eye random number generator and checker. As a result, the memory interface may be evaluated for electrical and timing specifications under a relatively simple test setup and test procedure through the test interface (JTAG), as opposed to a complex processor program that sets up a similar memory access pattern on Automated Test Equipment (ATE).

Memory interface with selectable evaluation modes

A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.

Growing community of inventors

Watertown, MA, United States of America

Thucydides Xanthopoulos