Infineon Technologies Ag

Intel Corporation

Intel Mobile Communications Gmbh

Infineon Technologies Austria Ag

Intel Deutschland Gmbh

Qimonda Ag

Thorsten Meyer

Harry Hedler

Markus Brunnbauer

Gerald Ofner

Andreas Wolter

Christian Geissler

Sven Albers

Jens G Pohl

Martin Gruber

Recai Sezi

Thorsten Scharf

Roland Irsigler

Reinhard Mahnkopf

Barbara Vasquez

Hans-Joachim Barth

Georg Seidemann

Stephan Bradl

Franz Hirler

Christoph Kadow

Norbert Krischke

Andreas Augustin

Klaus Pressel

Bernd Waidhas

Irmgard Escher-Poeppel

Andreas Peter Meiser

Maciej Wojnowski

Markus Zundel

Frank Dieter Pfirsch

Walter Rieger

Gerd Frankowsky

Wolfgang Klein

Klaus Reingruber

Josef Hoeglauer

Alexander Heinrich

Thomas Bemmerl

Ludwig Heitzer

Horst Theuss

Edward Fuergut

Armin Willmeroth

Frank Singer

Till Schloesser

Gottfried Beer

Xaver Schloegel

Vijay K Nair

Uwe Wahl

Rudolf Lachner

Mikael Bergholz Knudsen

Markus Schmitt

Peter Strobel

Sonja Koller

Josef Boeck

Richard Patten

Peter Scherl

Carolin Tolksdorf

Thomas Behrens

Pablo Herrero

Ralf Otremba

Rainer Leuschner

Yen Hsiang Chew

Walter Hartner

Sanka Ganesan

Kooi Chi Ooi

Peter Irsigler

Rainer Markus Schaller

Franz Jost

Andreas Grassmann

Carsten Schaeffer

Markus Dinkel

Howe Yin Loo

Dirk Hammerschmidt

Joachim Mahler

Telesphor Kamgaing

Robert L Sankman

Eung San Cho

Klaus Elian

John Stephen Guzek

Khalil Hosseini

Volker Lehmann

Klaus Schiess

Helmut Strack

Wolfgang Werner

Georg Meyer-Berg

Ivan Nikitin

Carsten Ahrens

Chuan Hu

Manfred Schneegans

Thomas Wagner

Olaf Hohlfeld

Ingo Muri

David Tumpold

Peter Baumgartner

Helmut Brech

Bernd Goller

Chau Fatt Chiang

Dominic Maier

Edmund Riedl

Swee Kah Lee

Heinrich Koerner

Oliver Hellmund

Philipp Riess

A method of fabricating a semiconductor device package includes: providing a die carrier; disposing at least one semiconductor die on the die carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier; electrically connecting the semiconductor die or another electrical device with an electrical connector; applying an encapsulant above the semiconductor die, the die carrier, and the electrical connector; and screwing a metallic drilling screw through the encapsulant so that an end of the drilling screw contacts the electrical connector.

Method for fabricating a semiconductor device package comprising a pin in the form of a drilling screw

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Integrated circuit package having wirebonded multi-die stack

A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

Semiconductor package with metal posts from structured leadframe

A radiation source device includes at least one membrane layer, a radiation source structure to emit electromagnetic or infrared radiation, a substrate and a spacer structure, wherein the substrate and the at least one membrane form a chamber, wherein a pressure in the chamber is lower than or equal to a pressure outside of the chamber, and wherein the radiation source structure is arranged between the at least one membrane layer and the substrate.

Radiation source device

A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.

Semiconductor packages including electrical redistribution layers of different thicknesses and methods for manufacturing thereof

A method of manufacturing a semiconductor body includes forming a pattern at a first side of a substrate, forming a semiconductor layer on the first side of the substrate, attaching the substrate and the semiconductor layer to a carrier via a surface of the semiconductor layer, and removing the substrate from a second side opposite to the first side.

Semiconductor device having contact trenches extending from opposite sides of a semiconductor body

A semiconductor device includes a semiconductor die having an active main surface and an opposite main surface opposite the active main surface. The semiconductor device further includes an antenna arranged on the active main surface of the semiconductor die and a recess arranged on the opposite main surface of the semiconductor die. The recess is arranged over the antenna.

Semiconductor device having an antenna arranged over an active main surface of a semiconductor die

Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Vertical inductor for WLCSP

The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector.

Semiconductor device package comprising a pin in the form of a drilling screw

A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.

Package with elevated lead and structure extending vertically from encapsulant bottom

A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.

Package with separate substrate sections

A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.

Flat lead package formation method

A semiconductor device includes a semiconductor die, an electrical contact arranged on a surface of the semiconductor die, and a metal layer arranged on the electrical contact, wherein the metal layer includes a singulated part of at least one of a metal foil, a metal sheet, a metal leadframe, or a metal plate. When viewed in a direction perpendicular to the surface of the semiconductor die, a footprint of the electrical contact and a footprint of the metal layer are substantially congruent.

Semiconductor device including an electrical contact with a metal layer arranged thereon

The disclosure describes to techniques for detecting field failures or performance degradation of circuits, including integrated circuits (IC), by including additional contacts, i.e. terminals, along with the functional contacts that used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, temperature and impedance. These electrical characteristics may be representative of a certain failure mode and may be an indicator for circuit state-of-health (SOH), while the circuit is performing in the field.

Predictive chip-maintenance

A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

Clip frame assembly, semiconductor package having a lead frame and a clip frame, and method of manufacture

Growing community of inventors

Wuppertal, Germany

Thorsten Meyer