Infineon Technologies Ag

Elpida Memory, Inc.

Thorsten Hinderer

Eric Pihet

David Astrom

Maximilian Mangst

Matthias Stecher

Maksim Kuzmenka

Hermann Gruber

Ulrich Glaser

Norliza Morban

Markus Hopfner

Jens Repp

Fortunato Lopez

Eric Lopez Bonifacio

Andrei Negoita

A differential feedback circuit with an active noise cancelation technique using a dual input differential pair. In the differential feedback circuit, a feedback voltage and a reference voltage connect to a primary input pair. Sensed noise at the inputs is put to a secondary input pair of the differential amplifier, which is inverted with respect to the primary input pair. In other words, the reference voltage, which may be subject to noise, connects directly to one terminal of the secondary input pair and through a low-pass filter to another terminal of the secondary input pair so that the noise, which may be coupled to the differential feedback circuit, cancels at the output of the differential feedback circuit.

Active ground bounce noise cancelation technique for closed loop analog regulation

A transmitter circuit for a field bus driver includes a first bus terminal and a second bus terminal for connecting a first bus line and, respectively, a second bus line. The transmitter circuit further includes a first supply terminal for receiving a supply voltage and second supply terminal for receiving a reference voltage, a first switching circuit coupled between the first supply terminal and the first bus terminal, and a second switching circuit coupled between the second bus terminal and the second supply terminal. The first switching circuit includes a first transistor and a second transistor, and the second switching circuit includes a third transistor and a fourth transistor. Further, the transmitter circuit comprises control circuitry configured to generate first drive signals for the first transistor and the third transistor and second drive signals for the second transistor and the fourth transistor based on a transmit signal.

Field bus driver circuit

A device including a first voltage domain and a second voltage domain is provided, the voltage domains being separated by an isolation barrier. In addition, the device includes a scratch detection circuit including a first and a second electrode at a distance of less than 2 &#x3bc;m.

Device comprising two voltage domains and method

A lead frame includes a first die paddle, a second die paddle, a first lead, a second lead, and a third lead. The first lead is coupled to a first side of the first die paddle. The second lead is coupled to a second side of the first die paddle opposite to the first side of the first die paddle. The third lead is coupled to a first side of the second die paddle. At least one of the first lead, the second lead, and the third lead is coupled to the corresponding die paddle via a zigzag shaped tie bar.

Lead frames for semiconductor packages

A circuit includes electrostatic discharge (ESD) protection circuitry, triggering circuitry, transient detection circuitry, and deactivation circuitry. The ESD protection circuitry is coupled between a first rail and a second rail. The triggering circuitry is configured to generate an ESD activation signal when a voltage across the first rail and the second rail exceeds a voltage threshold. The ESD protection circuitry is configured to activate based on the ESD activation signal. The transient detection circuitry is configured to generate a deactivation signal when the voltage across the first rail and the second rail comprises a voltage change over time that is less than a transient threshold. The deactivation circuitry is configured to deactivate the triggering circuitry based on the deactivation signal.

Active ESD clamp deactivation

The description that follows relates to a circuit having galvanic isolation. According to an exemplary embodiment, the circuit has a transmission circuit, coupled to a galvanically isolating device, that is designed to transmit a first signal via the galvanically isolating device. The circuit further has a first receiver circuit, coupled to the galvanically isolating device, that is designed to receive the transmitted first signal from the galvanically isolating device. A second receiver circuit coupled to the galvanically isolating device is designed to receive the transmitted first signal from the galvanically isolating device and to take the received first signal as a basis for generating a wake-up signal.

Interface circuit

A method for a bus interface circuit is described. According to one exemplary embodiment, the method comprises coding a first data stream by assigning first symbols to falling and rising edges of the first data stream, and coding a further data stream by assigning second symbols to the edges or levels of said further data stream. A symbol sequence is constructed from the first symbols and second symbols, wherein said symbol sequence is constructed in such a manner that the first symbols are always delayed by the same value relative to the associated edges of the first data stream. The method also comprises transmitting the symbol sequence via a galvanically isolating component, and decoding the symbol sequence transmitted via the galvanically isolating component in order to reconstruct the first data stream and the further data stream.

Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.

Differential bus receiver with four-quadrant input circuit

A method for synchronizing a data signal in a bus environment is suggested, the method may include providing multiple clock phases based on a reference oscillator; determining a phase out of the multiple clock phases for a transition of a data signal; and synchronizing the data signal based on the phase determined.

Synchronization of a data signal

A differential stage circuit is disclosed, which includes a differential circuit, a current source coupled to supply, when activated, an operating current to the differential circuit, and a control circuit coupled to control activation and deactivation of the current source. The differential stage circuit further includes a compensation circuit configured to supply a compensation pulse to the current source when the current source is activated.

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Neubiberg, Germany

Thorsten Hinderer