Silex Microsystems Ab

Silex Microsystem Ab

Silex Microsystems Ag

Thorbjörn Ebefors

Niklas Svedin

Edvard Kälvesten

Tomas Bauer

Daniel Perttu

Anders Eriksson

Peter Agren

Thierry Corman

Henrik Knutsson

Edward Kalvesten

Pelle Rangsten

Thomas Ericson

Edward Kälvesten

Hakan Westin

Tommy Schönberg

Peter Ågren

Edward KÄLVESTEN

Thomas Bauer

Edvard KÄLVESTEN

Håkan Westin

Tommy Huhtaoja

A method of providing a metal coating on a substrate (), and electrically insulating sections/parts of the metal coated substrate from each other. A substrate is provided with an insulating material in the substrate, the insulating first material extending through the thickness of the substrate and protruding above one surface of the substrate. It forms an enclosed section/portion () of the substrate. A protective structure () is provided on the insulating material such that it covers the entire circumference thereof. The insulating material is selectively etched to create an under-etch () under the protective structure. Finally conductive material () is deposited to provide a metal coating over the substrate, whereby the under-etch will provide a disruption in the deposited metal coating, thereby electrically insulating the enclosed section from the surrounding substrate.

Insulation of micro structures

A device includes a base substrate () with a micro component () attached thereto. Suitably it is provided with routing elements () for conducting signals to and from the component (). It also includes spacer members () which also can act as conducting structures for routing signals vertically. There is a capping structure () of a glass material, provided above the base substrate (), bonded via the spacer members (), preferably by eutectic bonding, wherein the capping structure () includes vias () including metal for providing electrical connection through the capping structure. The vias can be made by a stamping/pressing method entailing pressing needles under heating to soften the glass and applying pressure, to a predetermined depth in the glass. However, other methods are possible, e-g- drilling, etching, blasting.

Thin capping for MEMS devices

A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

Method of making a semiconductor device having a functional capping

A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings &#x3c;10 &#x3bc;m are provided on both sides of the wafer.

Method for forming electroless metal through via

Electroless metal through silicon via

A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.

Thin film capping

The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.

Semiconductor devices with close-packed via structures having in-plane routing and method of making same

A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.

Via structure and method thereof

A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is &#x3c;300 &#x3bc;m.

Method of providing a via hole and routing structure

The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (). It comprises providing a wafer () having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base () having a high resistivity top layer () suitable for semiconductor engineering, characterized by having low resistivity wafer through connections ().

Methods for making a starting substrate wafer for semiconductor engineering having wafer through connections

The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter, &#x3c;1:1, preferably 1:1 to 2:1.

CTE matched interposer and method of making

A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.

Growing community of inventors

Huddinge, Sweden

Thorbjörn Ebefors