Siemens Aktiengesellschaft

Infineon Technologies Ag

Thoralf Gr&auml;tz

Patrick Heyne

Dieter H&auml;rle

Bret A Johnson

Helmut Schneider

Helmut Fischer

The optimized-delay multiplexer includes at least two pass elements that are respectively driven via a first path by a control signal directly, and via a second path by the control signal inverted by an inverter. A further pass element is connected in the first path to simulate the delay caused by the inverter. As a result, the at least two pass elements are switched simultaneously.

Optimized-delay multiplexer

A semiconductor memory of the dynamic random access type (DRAM) includes memory cells combined in addressable units of bit lines and word lines. Each memory cell array is allocated a row decoder for selection of one of the word lines and a column decoder for selection of one of the bit lines, in the memory cell array. The row decoder is connected to a row selection signal line for transmission of a selection signal. The row decoder is disposed at an edge of the memory cell array allocated thereto, and between the memory cell arrays. The column decoder is connected to the row selection signal line. The column decoder is disposed on the outer edge area both of the memory cell array allocated thereto and of the memory field. A method for actuating a memory cell in such a semiconductor memory is also provided.

Semiconductor memory of the dynamic random access type (DRAM) and method for actuating a memory cell

The circuit configuration produces complementary signals. An input signal is routed from an input terminal via a first path, through a pass element, and to a first output terminal. The input signal is also routed on a second path, connected in parallel with the first path, via an inverter, and to a second output terminal. The first and the second output terminal are connected to a first and a second output node, respectively, via a compensation device. The compensation device compensates for the different time delays in the signals on the first and on the second path.

Circuit configuration for producing complementary signals

A dynamic memory includes memory cells combined to form blocks and blocks combined to form at least one block group. The memory also includes bit lines and word lines connected to the memory cells for selecting the memory cells, redundant memory cells within the blocks, at least one redundant word line in at least one of the blocks, and a decoder unit connected to the word lines. The redundant word lines are connected to the redundant memory cells for selecting the redundant memory cells. A redundant word line, after redundancy programming has been carried out, selectively replaces a word line in any of the blocks. In a first mode of operation, no more than one of the word lines is selected simultaneously per block group. In a second mode of operation, more than one of the word lines is selected simultaneously per block group, and redundancy programming is deactivated.

Growing community of inventors

Dresden, Germany

Thoralf Grätz

Growing community of inventors

Dresden, Germany

Thoralf Gr&auml;tz

Thoralf Grätz