Tandem Computers Incorporated

Synopsys, Inc.

Silvaco, Inc.

Thomas Warren Savage

Shivakumar Shankar Chonnad

Jeffrey Allen Roberts

Manickam E Kandaswamy

Michael Cizl

Christopher A Kopetzky

Maulin Bhatt

Embodiments disclosed include computer implemented systems and methods comprising multiple computer programs that when used together as part of the system enable the detection of one set of computer files within another set of files without having direct access to the files themselves. A computer program generated unique fingerprint for each set of files that is a condensed representation of that file that ensures no reverse engineering is possible from its use. Another computer program serves as a public repository to securely store fingerprints from multiple sources (e.g. companies).Additionally, another computer program is used to analyze the two or more file sets and produces a report that shows whether files in one set are contained in the other.

System and method for IP fingerprinting and IP DNA analysis

An HDL-based ASIC design is translated from a first RTL description to a second RTL description. The first RTL description describes the HDL-based ASIC design through a first set of modules arranged in a hierarchical manner. Translation includes: creating a reference gate-level netlist by synthesizing the HDL-based ASIC design described using the first RTL description; creating a second set of modules by translating the first RTL description of the first set of modules to the second RTL description module by module; and creating a combined RTL and gate-level design by integrating at least one module from the second set of modules within the reference gate-level netlist. Each module translated into the second RTL description may be also checked for compilation warning or error messages. If any warning or error messages are generated, the offending module(s) is modified to eliminate the warning or error messages. In addition, each module described using the first RTL description may be functionally compared with each module described using second RTL description. If any functional discrepancy exists between corresponding first and second RTL modules, the offending module described using the second RTL description is modified to rectify the functional discrepancy. Top-level simulation may be also performed on all of the modules that are described using the second RTL description.

Code translation between hardware design languages

An automatic addressing technique for flexibly specifying the individual physical addresses of a plurality of devices coupled to an information bus. An anchor pattern is applied to an address bus of a plurality of address taps sufficient to uniquely specify the numbered J of devices to be attached thereto. Each device is connected to a tap on the address bus, each tap having the same number of bits. A plurality of address transform elements are serially connected to the bus, each transform element being located between adjacent tap positions. Each transform element converts the address pattern coupled to its input to another pattern capable of uniquely specifying the next address in the desired sequence. A wide variety of address sequences are available for selection, with each particular address sequence automatically determined by the related specific anchor pattern. The transform elements are passive elements, and no jumpers or settable switches are required to specify the physical addresses when configuring or reconfiguring the system.

System for specifying addresses by creating a multi-bit ranked ordered

A boundary scan bus error reporting circuitry loads an unused sentinel bit pattern into the boundary scan instruction register in a conventional error reporting boundary scan test system. The unused sentinel bit pattern signifies that a fault exists somewhere upstream of the instruction register in the boundary scan circuitry associated with a specific integrated circuit. The special sentinel pattern is loaded into the instruction register in response to an illegal instruction control signal generated by an instruction decoder coupled to the instruction latch in the boundary scan architecture.

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San Jose, CA, United States of America

Thomas Warren Savage