Texas Instruments Corporation

Thomas Warren Lassiter

Neng Jiang

Joel Soman

Mary Alyssa Drummond Roby

YungShan Chang

Nayeemuddin Mohammed

Xin Li

Scott Robert Summerfelt

Bruce E Flinchbaugh

Aditya Srivastava

Sarma S Gunturi

Maciej Blasiak

Simon Y S Chang

Steven B Dolins

Jamie T Stapleton

Robert L Love

A microelectronic device containing a piezoelectric thin film element is formed by oxidizing a top surface of a piezoelectric layer with an oxygen plasma, and subsequently forming an etch mask containing photoresist on the oxidized top surface. The etch mask is conditioned with an oven bake followed by a UV bake. The piezoelectric layer is etched using a three step process: a first step includes a wet etch of an aqueous solution of about 5% NHF, about 1.2% HF, and about 18% HCl, maintaining a ratio of the HCl to the HF of about 15.0, which removes a majority of the piezoelectric layer. A second step includes an agitated rinse. A third step includes a short etch in the aqueous solution of NHF, HF, and HCl.

Method of forming a semiconductor device

A method includes placing a device having a titanium nitride layer into a chamber. The device also has a mask that includes a photoresist material and an aluminum copper hardmask. The method also includes performing an ashing process on the mask using the chamber. The method further includes, after the ashing process, performing an etching process using the chamber to etch through portions of the titanium nitride layer. Performing the etching process includes flowing a gas mixture containing tetrafluoromethane (CF) and oxygen gas (O) into the chamber at a temperature of at least about 200&#xb0; C.

High-temperature isotropic plasma etching process to prevent electrical shorts

Piezoeletric wet etch process with reduced resist lifting and controlled undercut

An apparatus includes first and second electrodes separated by an insulative material (such as a piezoelectric material). The apparatus also includes a protective layer over the first and second electrodes. The protective layer has a first opening that exposes a portion of the first electrode and a second opening that exposes a portion of the second electrode. The apparatus further includes a first electrical contact at least partially within the first opening and electrically coupled to the first electrode. In addition, the apparatus includes a second electrical contact at least partially within the second opening and electrically coupled to the second electrode. Each of the first and second electrical contacts includes a stack of metal layers. The stack of metal layers includes a titanium nitride layer, a titanium layer over the titanium nitride layer, and an aluminum copper layer over the titanium nitride layer and the titanium layer.

Bond-pad integration scheme for improved moisture barrier and electrical contact

Methods and apparatus for forming structures to reduce wafer warpage. A method includes providing a semiconductor wafer having a plurality of integrated circuits; providing a photomask defining a plurality of cavities to be formed by an etch on a backside surface of the semiconductor wafer; defining structural support areas for the backside surface, the structural support areas being contiguous areas; providing areas on the photomask that correspond to the structural support areas, the structural support areas being areas that are not to be etched; using the photomask, performing an etch on the backside surface of the semiconductor wafer to form the cavities by removing semiconductor material from the backside surface of the semiconductor wafer; and the structural supports on the backside of the semiconductor wafer formed as areas that are not subjected to the etch. Additional methods and apparatus are also disclosed.

Methods and apparatus to reduce semiconductor wafer warpage in the presence of deep cavities

An improved apparatus and process for detecting aberrations in production process operations is provided. In one embodiment, operations of a plasma etch reactor (10) are monitored to detect aberrations in etching operations. A reference end-point trace (EPT) is defined (62) for the etch process. Regions are defined in the reference end-point trace (70) and characteristics and tolerances for each region are defined (72-80). The etcher is run and an actual EPT is obtained (82) from the running of the etcher. The actual EPT is analyzed to identify proposed regions of the actual EPT (86), and then the proposed regions of the actual EPT are matched with regions of the reference EPT (96). The system employs a series of heuristic functions in matching proposed regions of the actual EPT with regions of the reference EPT. Characteristics of the matched regions of the actual end-point trace are compared (66) with characteristics of the corresponding regions of the reference end-point trace to determine whether aberrations have occurred during the etch process. The invention provides for an improved matching and improved comparison of actual end-point traces with reference end-point traces.

Process and apparatus for detecting aberrations in production process

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Garland, TX, United States of America

Thomas Warren Lassiter