Applied Integrated Systems & Software

Pdf Solutions, Incorporated

Thomas Waas

Hans Eisenmann

Hans Hartmann

Wojciech P Maly

Hans-Juergen Brueck

Michal Palusinski

Mariusz Niewczas

Andrezej Strojwas

A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.

Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout

A method of correcting physically conditioned errors in the measurement of an object detects an image of the object to be measured, measures the imaged object, determines a measurement error caused by structural surroundings of the object, and corrects the measurement result in dependence on the measurement error.

Method of correcting physically-conditioned errors in measurement of microscopic objects

A method for generating information for producing a pattern, defined by design information on a medium, using at least one direct-writing pattern generating process, which first provides the design information and then calculates correction data based on the provided design information and depending on the pattern generating process which corrects pattern faults in the pattern to be generated which were caused by the pattern generating process. The design and correction information is then separately provided to the direct-writing pattern generating process for its activation.

Procedure for generating information for producing a pattern defined by

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Munich, Germany

Thomas Waas