Micron Technology Incorporated

Aptina Imaging Corporation

Micron Display Technology, Inc.

Thomas W Voshell

Glen Earl Hush

Kevin G Duesman

Lucien J Bissey

David A Cathey

Stephen L Casper

Chen Hui Xu

David A Zimlich

Karl H Mauritz

Michael S Cohen

R Brent Lindsay

Karl W Holtzclaw

Charles W Tillinghast

Lisa J Davis

Brent Keeth

Troy A Manning

Terry R Lee

Kevin J Ryan

Chris G Martin

Wallace E Fister

Kim M Pierce

James M Shaffer

Geary L Leger

Mike Pearson

Chris A Unrein

A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Random access memory device utilizing a vertically oriented select transistor

Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory device having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.

Method, apparatus and system, providing a one-time programmable memory device

Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.

Method, apparatus and system providing a one-time programmable memory device

A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.

Method and apparatus for redundant location addressing using data compression

Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array. The peripheral circuitry can include a clock/control circuit providing a control signal, which controls when a row of memory cells are sensed, a switching circuit for receiving a cellplate count signal and a bit count signal provided by the clock/control circuit, a cellplate line signal and a bit line signal from the memory cell, the switching circuit producing a first output signal and a second output signal, wherein one of the first output signal and the second output signal is at a supply voltage and the other of the first output signal and the second output signal alternates polarity with each sensing operation and a comparison circuit receiving the first output signal and the second output signal and outputting a signal corresponding to the logic sate of the memory cell.

AC sensing for a resistive memory

Method of fabricating a random access memory device utilizing a vertically oriented select transistor

A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Programmable pulse generator and method for using same

A method and a control circuit for controlling a field emission display to reduce emission to grid during turn on and turn off are provided. In an illustrative embodiment, the control circuit includes a threshold detector that receives an input signal proportional to an anode voltage (V,) for the display and produces a high or low output signal dependent on the level of V,. An output low corresponding to a high voltage at the display screen enables a gate element of a pass transistor that controls current flow to the grid. Alternately, an output high corresponding to a low voltage at the display screen enables a pull down transistor that controls discharge of the grid to ground. The control circuit can also include a fault detection circuit for detecting a sharp decrease in the anode voltage and discharging the grid. In an alternate embodiment, the control circuit shorts the emitter sites together during turn on and turn off and provides a high source impedance to restrict current flow to any one emitter site. The high source impedance can be permanent or switchable by a relay or switching circuit.

Method and circuit for controlling a field emission display for reducing emission to grid

Method and apparatus for redundant location addressing using data

A single ended read data path in a memory device is described for providing a data signal from a cell in a memory array to a data output terminal. A single conductive path couples the data signal between a DC sense amplifier and a data output circuit in the memory device.

Method and apparatus for coupling data from a memory device using a

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Boise, ID, United States of America

Thomas W Voshell