National Semiconductor Corporation

Other

Thomas W Thomson

Ralph W Haines

Gary D Phillips

D Kevin Covey

Mario D Nemirovsky

Alexander Perez

Hon-Kai John Tam

HonKai John Tam

A two mass, single motor bi-directional conveyor for conveying solid objects, granular and powder material. The unit utilizes the two mass sub-resonant natural frequency system driven by a single motor with counterweight wheels. The forces created by the rotation of the counterweight wheels results in a trough stroke at an angle from the horizontal pan resulting in material motion. The trough stroke is absorbed with isolation springs mounted between the conveyor and the ground.

Single motor two mass bi-directional conveyor

A bit searching method shifts an operand and counts the number of shifts it takes to shift out the value one, thereby identifying the bit position in operand containing the value one. The operand is first compared to zero. If the operand is zero, the zero flag is set, otherwise, a register is initialized by being cleared for a bit search forward instruction or, for a bit search reverse instruction, being initialized to 15 for a 16-bit data length or 31 for a 32-bit data length For a bit search forward instruction, the operand is then shifted right one bit and the register is incremented, while for a bit search reverse instruction, the operand is shifted left one bit and the register is decremented. The operand is then examined to see if a 1 has been shifted out. If so, the register is read and decremented by 1 to yield the bit position of the operand where the first 1 was found. If not, then another shift and increment (decrement) step is performed.

Bit searching through 8, 16, or 32 bit operands using a 32 bit data path

A double precision shift operation utilizes a 32 bit data path.

Double precision (64 bit) shift operations using a 32 bit data path

A microprocessor execution unit includes an arithmetic unit and an addressing unit. The arithmetic unit performs arithmetic and logical operations on operands. The addressing unit operates in conjunction with the arithmetic unit to calculate offsets, limits, and linear addresses in a single cycle.

Execution unit architecture to support X86 instruction set and X86

A barrel shifter performs multi-bit shift and rotate operations on data of different lengths using multiplexors to preprocess the data prior to introducing the data to a transistor array.

Barrel shifter

A CAN node having an enhanced fault recovery system is disclosed. The CAN node includes a CAN protocol controller device which reconnects to a CAN bus from the node's busoff state only after the node has successfully decoded 128 good messages from other devices on the CAN bus. Such a system advantageously provides a CAN node which exits its busoff state with a high degree of confidence that the fault that caused the node to enter the busoff state has been cleared. The protocol controller device uses the eleven recessive bits that start at the acknowledgement delimiter and finish at the end of the third bit of intermission to recognize that a single message has been successfully decoded.

Can interface with enhanced fault confinement

A CAN node with a CAN protocol controller device reconnects to a CAN bus from the node's busoff state only after the node has successfully decoded a plurality of good messages from other devices on the CAN bus. Reception of a plurality of good messages advantageously provides a CAN protocol controller device which exits its busoff state with a high degree of confidence that the fault that caused the node to enter the busoff state has been cleared.

Can interface selecting one of two distinct fault recovery method after

A method for summing a sequence of binary product terms utilizing a modified Booth's algorithm in an arithmetic unit, wherein the arithmetic unit has a multiplicand register, a multiplier register, a data bus coupled to the multiplicand register and to the multiplier register, a pad bit located adjacent to the least signficant bit of the multiplier register, and an adder register coupled to the multiplicand register. After initializing the adder register, the values of the pad bit and the two least significant bits of the multiplier register are examined and a modified Booth's algorithm is performed on the data in the multiplicand register based on the examined values. The multiplier value is then shifted 2 places to the right, through the pad bit, and the multiplicand value is shifted 2 places to the left. The values of the pad bit and the two least significant bits of the multiplier register are again examined and a modified Booth's algorithm is performed on the data in the multiplicand register based on the shifted examined values.

Combined multiplier and accumulator

An arithmetic unit for multiplying and accumulating signed binary data and indicating an occurrence of a signed arithmetic overflow includes a multiplier-accumulator and an overflow flag register. The multiplier-accumulator receives and selectively multiples and accumulates signed binary data, and provides output data representing the multiplied and accumulated data and a sign bit representing its polarity, i.e. positive or negative. The flag register provides two 'sticky' flag bits for indicating whether a signed arithmetic overflow (positive or negative) of the multiplied and accumulated data has occurred. The flag bits are 'sticky' in that once a flag has been set, it cannot be reset by another arithmetic overflow condition. Instead, it must be specifically reset. The sign bit is used to selectively set one of the two sticky flag bits to a true state to indicate the direction (positive or negative) of the first arithmetic overflow. The sticky flag bits have mutually exclusive true states in that once a flag bit has been set true, the other flag bit cannot be set true until both flag bits have been specifically reset.

Signed overflow sticky bits

An integrated circuit (IC) processor architecture is disclosed that implements hardware, signal processing (DSP) functions with less digital improved speed and a more efficient layout. The resources of the central processing unit (CPU) are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Internal registers of the CPU are used to store pointers which reference a circular sample buffer. The CPU thus manages the selection and transfer of coefficients from the sample buffer to the multiply/accumulate unit, thereby allowing a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permitting DSP operations to be performed in parallel with CPU operations.

CPU with integrated multiply/accumulate unit

An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms. Instead of clearing the adder of the result of one multiplication before beginning another, the result is maintained and all subsequent partial products are added to it to generate a final output. The placement of the 32-bits of the multiply/accumulate unit's multiplicand register is arranged in two rows of 8 even bits and two rows of 8 odd bits to allow left shift by two with a single loop around and to provide direct interface with the 16-bit data latch register on its input and the rest of the 32-bit arithmetic logic unit (ALU) on its output.

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Santa Cruz, CA, United States of America

Thomas W Thomson