Apple Inc.

Microelectronics and Computer Technology Corporation

Intrinsity, Inc.

Thomas W Rudwick, Iii

James S Blomgren

Timothy A Olson

Robert F Miracky

Donald W Glowka

Jeffrey B Reed

Scott C Sommerfeldt

A system and method for persisting object pointers in a computing system. Subsequent to initiating an operation to store a plurality of memory resident objects from a memory to persistent storage, a first object of the objects is accessed. Each of the objects may include pointers to other objects in memory. An object identifier is created for the object and stored within the first object. References within the first object to other objects are replaced with object identifiers created for the referenced objects. When an object identifier is created and stored within an object, existing data within the object is replaced by the identifier. The replaced data is stored in a data structure along with a pointer to the object in memory. Subsequent to storing the objects to persistent storage, the data structure is used to restore the replaced data to the objects in memory.

System and method for persisting object pointers

The matching algorithm of the layout synthesis method and apparatus disclosed locates transistor pattern matches in a design, links a parameterized tile to each identified match, and adjusts certain variable parameters of the linked parameterized tile to meet the physical design requirements of each located match. Each transistor pattern corresponds to a parameterized tile, which is an actual physical representation of the corresponding pattern and includes variable parameters, which may include transistor size. The matching algorithm locates matches in the design for an ordered list of patterns, names each located match, links the proper parameterized tile to each named match, and adjusts the tile's variable parameters as required. Transistors in the design are included in one and only one named located match.

Physical realization of dynamic logic using parameterized tile partitioning

Provided is an electrical interconnect cell intermittently spaced across a substrate to form an interconnect device or structure. The interconnect device is fully customizable or programmable upon the upper surface to accommodate various electrical components and connectivity to those components. The electrical interconnect device includes a plurality of intermittently spaced first pairs of upper and lower signal lines interwoven with a plurality of intermittently spaced second pairs of upper and lower signal lines. A bonding pad is arranged between adjacent upper and lower signal line pairs and can be connected thereto with conductive links placed upon the surface layer. Each bonding pad includes one or more pad vias which extend perpendicular to the upper surface to conductive structures arranged in lower layers. Approximately one-half of the array of bonding pads are connected to potential conductors. The pairs of upper signal lines can not only be linked, but also can be cut to form a more direct routing between target locations. Moreover, the upper and lower signal lines are connected in order for traces to extend across the entire interconnect structure for ease of testability.

Electrical interconnect device with customizeable surface layer and

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Austin, TX, United States of America

Thomas W Rudwick, Iii