Ericsson Gmbh

Infineon Technologies Ag

Telefonaktiebolaget Lm Ericsson (publ)

Ericcson Inc.

Thomas W Moller

Larry C Leighton

Bengt Ahl

Henrik Hoyer

Jan H Johansson

William Hart

Cynthia Blair

Prasanth Perugupalli

Nagaraj V Dixit

Jan Johansson

Nils Af Ekenstam

Robert Bartola

Timothy Ballard

Gary Lopes

Michael Peternel

James Mogel

Jeff Hume

Tan Pham

Cindy Blair

Nagaraj Vishwanath Dixit

A power transistor, having: a semiconductor having an electrode formed thereon, wherein the electrode comprises a plurality of interdigitated transistors each having input and output terminals; a first output blocking capacitor having a first terminal electrically coupled to the output terminals of the interdigitated transistors of the semiconductor and a second terminal electrically coupled to ground; and a second output blocking capacitor having a first terminal electrically coupled to the first terminal of the first output blocking capacitor and a second terminal electrically coupled to ground. A method for amplifying signals, the method having: forming a power transistor on a semiconductor, wherein the power transistor comprises a plurality of interdigitated transistors; shunting an output signal from the plurality of interdigitated transistors; and double-shunting an output signal from the plurality of interdigitated transistors, wherein the shunting and double-shunting generates first and second harmonic terminations at a die plane of the power transistor.

Output match transistor

Linearity and/or efficiency of a power MOS transistor comprising a plurality of transistor segments connected in parallel, is improved in that at least one group of said transistor segments has a different threshold voltage than the rest of the transistor segments.

Arrangement in a power mosfet

A constant gain, constant phase RF power block, e.g., for use in a RF amplifier apparatus. In a preferred embodiment, the power block includes a DC to DC power supply circuit co-located with an RF power transistor device on a common heat sink. The power supply circuit has as an input a varying DC voltage and as outputs a constant supply voltage and a constant bias voltage. The power device has as inputs the constant supply voltage and the constant bias voltage, and further configured to receive and amplify an RF signal. The power supply circuit preferably includes a first laser trimmable resistor for setting the constant supply voltage and a second laser trimmable resistor for setting the bias voltage. In this manner, the constant supply and bias voltages may be easily tuned to a desired level during assembly of the power block device. The input and amplified RF signals are each matched to a relatively high impedance, e.g., approximately fifty ohms.

Constant gain, constant phase RF power block

A broadband RF signal amplifier includes a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output. An RF input path electrically connected to the transistor inputs includes a passive splitter implemented in a multi-layer printed circuit board and configured to split a RF input signal into a plurality of component input signals. A plurality of corresponding input matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple respective component input signals to the transistor inputs at an input impedance, the input matching networks further comprising respective input matching capacitors attached to the pedestal. An RF output path electrically connected to the transistor outputs includes a passive combiner implemented in the printed circuit board and configured to combine component output signals received at the transistor outputs into a RF output signal. A plurality of corresponding output matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple the respective component output signals at the transistor outputs to an output impedance.

Multi-stage, high frequency, high power signal amplifier

A desired performance characteristic of an electrical circuit employing a strip conductor is achieved by placing a fluid having a selected dielectric property in contact with at least a portion of the strip conductor, such that the dielectric property of the fluid effects one or more transmission characteristics of the conductor. In one embodiment, the circuit performance is measured and the dielectric property of the fluid adjusted, e.g., in an iterative process, until the desired performance characteristic of the circuit is achieved.

Liquid dielectric tuning of an integrated circuit

A plurality of conductors and an electrical component are disposed on a substrate, wherein the electrical component has a plurality of leads that are connected to the conductors on the substrate by a plurality of bond wires. A damping material is then situated in contact with the plurality of bond wires, the damping material chosen so that the plurality of bond wires can move in relation to the damping material. The damping material may be a viscous liquid kept in contact with the bond wires by a containing lid attached to the substrate. Alternatively, the damping material may be a colloidal mixture involving a liquid or an elastomer.

Liquid damping of high frequency bond wire vibration

An LDMOS power package includes a mounting substrate having a surface with one or more alignment pedestals extending therefrom. Each alignment pedestal has a mounting surface facing away from the substrate surface to provide for uniform positioning of various semiconductor elements, e.g., a transistor die or impedance matching capacitors, relative to the substrate surface. The respective pedestal mounting surfaces are preferably conductive, and are electrically coupled to the flange surface, so as to electrically couple the respective capacitor and electrode ground terminals to the flange.

Alignment pedestals in an LDMOS power package

A packaged integrated circuit device includes a substrate including a first circuit component mounted thereon, a first conductor extending from the first circuit component, and a dielectric lid. The dielectric lid includes a component mounting surface, a second circuit component mounted on the component mounting surface, and a second conductor extending from the second circuit component. The dielectric lid is adapted to engage with the substrate such that the first circuit component is in electrical communication with the second circuit component. The second circuit component may comprises an impedance matching circuit. The circuit device may also include fastening means for securing the lid to the substrate. The fastening means may comprise an adhesive, solder, or a spring biased member.

Functional lid for RF power package

An electrical assembly includes an IC package having a thermally conductive mounting flange in contact with a heat sink. A thermally conductive casing is secured to the heat sink, the casing at least partially enclosing the IC package. A resilient retaining member is disposed between the casing and IC package, the retaining member applying sufficient force on the IC package so as to maintain good thermal contact between the mounting flange and heat sink.

Thermally conductive mounting arrangement for securing an integrated circuit package to a heat sink

A thermally conductive mounting flange of an IC package is placed directly on a heat sink surface between respective sections of single layer PC board attached to the heat sink, such that electrical leads extending from opposing sides of the package are positioned over corresponding conductive areas formed on the surface of the respective adjacent PC board section. The leads are electrically coupled with the conductive areas by respective tie-down screws fastened through dielectric isolating washers. The screws are tightened sufficiently against the isolating washers so as to press the respective package leads into solid electrical contact with the conductive areas. Portions of the respective leads and conductive areas surrounding the tie-down screws are cut-away to prevent electrical contact, in order to avoid shorting the leads and/or conductive areas to the heat sink via the tie-down screws. Alternately, respective ends of a retaining spring used to secure the IC package to the heat sink mounting flange are also secured by the package lead tie-down screws, such that the screws both secure the package against the heat sink and press the package leads into solid electrical contact with the respective conductive areas.

Capacitive mounting arrangement for securing an integrated circuit

A plurality of transistor cells (36) formed on a semiconductor substrate (32) are connected to form a radio frequency power transistor device (30), whereby individual conductive paths (38) are formed on one side of the substrate (32) to connect respective common gate terminals (34) of adjacent transistor cells (36) in series. A further conductive path (40) is formed on an opposite side of the substrate connecting respective drain terminals (35) of the transistor cells (36) in parallel. A resistive element (42) is interposed in the conductive path (38) connecting each adjacent pair of gate terminals (34). The conductivity of the respective resistive elements (42) is selected so as to adequately provide a conductive pathway for connecting the respective gate terminal outputs, while being sufficiently resistive such that each gate terminal 34 'sees' an electrical circuit termination.

Resistive interconnect of transistor cells

A thermally conductive mounting flange of an IC package is placed directly on a heat sink surface between respective sections of single layer PC board attached to the heat sink, such that electrical leads extending from opposing sides of the package are positioned over corresponding conductive areas formed on the surface of the respective adjacent PC board section. The respective package leads are each connected to the corresponding PC board areas by one or more flexible bond wires. In addition to electrically connecting the package leads to the respective PC board sections, the bond wires collectively secure the package to the heat sink in a manner allowing for relative lateral movement between the respective flange and heat sink surfaces in response to thermal stresses.

Wire bond attachment of a integrated circuit package to a heat sink

An RF power transistor package is configured for mounting to a heat sink in a multi-layer pc board, and includes a direct top side electrical ground path from a transistor chip located atop a ceramic substrate to a mounting flange, without passing through the ceramic substrate by way of metal plating an outer surface of the ceramic substrate to electrically connect a top mounted metal lead to the flange. A direct ground path from the transistor chip to the mounting flange is also provided by way of plated via holes through the ceramic substrate. The top side ground path is also configured to connect with the middle ground reference layer of the multi-layer pc board when the mounting flange is secured to the heat sink, so that a unified ground potential is seen by the transistor at both the middle layer and heat sink. In this manner, the power transistor package is grounded at the same reference potential as other elements attached to the pc board, while still having the high performance characteristics provided by the ground path via holes.

RF power package with a dual ground

A semiconductor die is attached to a transistor package by a plurality of resilient clamping members, which are bonded at one end to a top surface of the semiconductor die and at another end to a stable surface, such as an emitter, collector, or base lead frame, of the transistor package. The shape and composition of the clamping members provides a resilient force that causes a bottom surface of the die to make and maintain substantially uniform and constant contact with the die attach area of the transistor package, e.g., a mounting flange or non-conductive substrate. The clamping members are preferably conductive and can conduct current from respective transistor cell locations on the die to the respective lead frames to which the clamping members are bonded.

Growing community of inventors

Gilroy, CA, United States of America

Thomas W Moller