Advanced Micro Devices Corporation

Advanced Micro Designs, Inc.

Thomas W Lynch

Brian D McMinn

Robert M Perlman

Salim Ahmed Shah

Smeeta Gupta

Steven D McIntyre

John G Bartkowiak

Mark A Ireton

Ashraf Ahmed

Tony Hurson

Christopher J Yard

Andrew Mills

Robert C Thaden

Prem Sobel

Glenn A Tamura

Raju Vesgesna

Stephen D McIntyre

Ken Tseng

A floating point unit is provided which conveys the rounding mode in effect upon dispatch of a particular instruction with that particular instruction into the execution pipeline of the floating point unit. Upon dispatch of a control word update instruction into the execution pipeline, the rounding mode is updated according to the updated control word provided for the control word update instruction. Instructions subsequent to the control word update instruction thereby receive the updated rounding mode as those instructions are dispatched. The updated rounding mode is available to the subsequent instructions prior to retiring the control word update instruction. The rounding mode is therefore updated without serializing the update. If the control word update instruction modifies the value in a field other than the rounding mode, the instructions subsequent to the control word update instruction may be discarded and re-executed subsequent to updating the control word register with the updated control word. In this manner, the control word update is effectively serialized for cases in which a field other than the rounding mode is updated.

Piping rounding mode bits with floating point instructions to eliminate serialization

A superscalar microprocessor appends a tag value to each floating point number. The tag value indicates whether the corresponding floating point number is a normal floating point number or a special floating point number. Additionally, the tag value indicates the type of special floating point number represented by the corresponding floating point number. The tag value is stored with the floating point number in a register file of the floating point unit. Tag values are also generated for floating point numbers read from memory. When a floating point core of a floating point unit receives operands from either the register file or memory, the floating point core examines the tag values to determine whether each operand is a normal floating point number or a special floating point number. If either operand is a special floating point number, the floating point core determines the type of special floating point number and applies any applicable special rules. By appending tag values to each floating point number, the floating point unit can quickly determine which floating point numbers are special floating point numbers and the type of special floating point number. This reduces the time necessary to identify floating point numbers and expedites the execution of floating point instructions.

Apparatus and method for tagging floating point operands and results for

A data cache and method for manipulating data in a microprocessor are disclosed. The data cache stores stack data within a stack memory separate from a cache line oriented storage used for non-stack data. Data may be pushed, popped, and accessed via an offset from the stack memory without generating main memory addresses. A load/store unit coupled to the data cache may be configured to perform the address generation associated with stack accesses in parallel with performing the access to the stack memory. If the corresponding data is not stored within the stack memory, then an access to the cache line oriented storage may be performed. Therefore, no time penalty is assessed for missing the stack memory. A stack memory is contemplated for use with respect to subroutine parameter passing. The calling routine may perform multiple push commands to place parameters for use by the subroutine onto the stack. The subroutine may then access and modify the parameters upon the stack. Finally, the calling routine may perform multiple pop commands to remove the parameters from the stack.

Data cache and method using a stack memory for storing stack data

A pipeline conveys a control word and a steering word with each instruction. The control word specifies the control signals for the instruction at each pipeline stage. The steering word specifies the routing of the instruction through the pipeline stages. Many pipeline modifications may be made by modifying the control words and steering words corresponding to the instructions. According to one embodiment, the execution pipeline within the microprocessor employs the control word/steering word method of pipeline control. Certain instructions do not perform any multiplication operations, and so may bypass the multiply pipeline stage or stages. Similarly, other instructions do not perform addition operations and may bypass the adder pipeline stage or stages. Still further, data movement and control update type instructions may bypass the pipeline all together and move directly to the result queue in the FPU. Additional instructions may be implemented in many cases by adding a control word and steering word for the instructions into the control word/steering word generation. Additional instructions may be implemented in this manner if the hardware within the pipeline can be used to implement the instruction.

Rapid pipeline control using a control word and a steering word

A floating point arithmetic unit is provided which effectuates arithmetic operations upon floating point numbers. A comparator unit, which may be implemented using a carry-skip chain, determines the relative magnitudes of the exponents of the floating point numbers to be operated upon. A first ripple carry subtractor unit formed within a first ripple carry shifter subtracts a first value corresponding to the exponent of a first of the floating point numbers from a second value corresponding to the exponent of a second of the floating point numbers. A second ripple carry subtractor unit formed within a second ripple carry shifter subtracts the second value from the first value. When certain lower order bit results of the exponent value subtraction operations of each ripple carry subtractor are obtained, the mantissa of the floating point number with the smaller exponent provided to one of the carry ripple shifters is shifted to the right by a number of positions dependent upon the lower order bit results. Effectuation of this shift operation begins before determining certain intermediate order and high order bit results of the subtraction operation. When certain intermediate bit results of the exponent subtraction operation are obtained, further shifting of the mantissa is effectuated before the highest order bit results of the subtraction operation are determined. A final shift operation is effectuated upon determining the highest order bit results of the ripple carry subtraction operation. An output signal from the comparator unit, which determines the relative magnitudes of the exponents of the two floating point numbers being operated upon, selects the shifted mantissa output from the ripple carry shifter associated with the mantissa of the floating point number with the smaller exponent. This shifted mantissa is provided to an input of an adder/subtractor unit.

Ripple carry shifter in a floating point arithmetic unit of a

A microprocessor has an interface between a reorder buffer and a floating point unit, including a retire signal provided by the reorder buffer and a valid signal provided by the floating point unit. When the reorder buffer detects a floating point instruction which is ready to be retired, the reorder buffer pulses the retire signal. When the floating point unit executes the floating point instruction and produces a corresponding instruction result, the floating point unit pulses the valid signal. Upon assertion of both the retire signal and the valid signal, the floating point instruction is retired by the floating point unit. The reorder buffer retires the floating point instruction upon asserting the retire signal. Either the valid signal or the retire signal may be asserted first (in a temporal sense) for the floating point instruction. The receiving unit for the signal asserted first stores the signal in a shift register until the receiving unit detects the particular floating point instruction. The received signal pulse is then associated with the particular floating point instruction. Additionally, the interface may include a cancel signal provided by the reorder buffer in cases in which a floating point instruction is canceled, as well as an exception signal provided by the floating point unit instead of the valid signal if the particular floating point instruction experiences an exception. Finally, the interface may include a pair of signals for synchronizing the floating point unit and the reorder buffer upon detection of a floating point synchronization instruction.

Interface for coupling a floating point unit to a reorder buffer

A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses the floating point instructions into one or more floating point operations and one or more integer operations such as memory load operations. The floating point operations are conveyed to the floating point unit. The memory load operations load the floating point operands of the floating point operations. Floating point operands that are wider than integer operands are handled by multiple memory load operations. Each memory load operation loads a portion of the floating point operand. The portions of the floating point operand are combined is a queue in the floating point unit. When the floating point unit has received the floating point operation and the memory operands that comprise with the floating point operand, the floating point unit dispatches the floating point instruction for execution. Floating point instructions that are too complex to be completed in one pass through the floating point execution pipeline are further parsed into a plurality of floating point operations by the floating point unit.

Hierarchical microcode implementation of floating point instructions for

Assembly queue for a floating point unit

A cache is provided which prefetches data words associated with a particular addressing mode. When a data word is accessed in response to the execution of an instruction, the data word is discarded by the cache. Data which is accessed in a use-once fashion (such as DSP data, for example) may be thereby available with cache-hit memory access times instead of main memory access times. The present cache prefetches data words spaced at regular or irregular intervals, wherein the interval is specified by the addressing mode of the instruction. Multiple words within a data stream may be successfully prefetched. The cache described herein may be incorporated into a microprocessor having a conventional cache as well. Data which is indicated to be used once may be stored in the present cache, while data exhibiting locality may be stored in the conventional cache. Data which exhibits locality is thereby retained within the cache system when use-once data is accessed.

Data cache configured to store data in a use-once manner

A microprocessor is provided which includes a heuristic processing unit configured to detect a predefined group of instructions and to cause the performance of a specific function associated with the group of instructions. The specific function may correspond to the outcome of executing the group of instructions. Alternatively, the specific function may be a set of operations not directly corresponding to the group of instructions, but designed to improve the performance of the sequence of instructions within which the group of instructions is embedded. The heuristic processing unit asserts control signals to dedicated hardware to cause the specific function to be performed. Instruction sequences need not be modified from the instruction set employed by the microprocessor. The microprocessor detects the previously inefficient instruction sequences and performs the corresponding function efficiently.

Microprocessor configured to detect a group of instructions and to

A computer system is provided which includes at least two microprocessors. The first microprocessor is configured to translate instructions from an original computer program coded in a first instruction set to a translated computer program coded in a second instruction set. The second microprocessor is configured to execute the translated program. In one particular embodiment, the original program is coded in the x86 instruction set and the translated program is coded in the ADSP 2171 instruction set. Instead of manually performing the translation, the translation is automatically performed by the computer system upon invocation of the original computer program. Those computer programs which may be more efficiently executed by the second microprocessor may be translated into the instruction set executed by the second microprocessor. In one embodiment, the translation of the computer program is performed in page-sized portions. The first microprocessor translates a first page of the original computer program. While the first microprocessor translates a second page of the original computer program, the second microprocessor begins execution of the first page of translated instructions.

Computer system configured to translate a computer program into a second

A processor employing a dynamically configurable bus interconnect is provided. The interconnect routes data between functional units and memories included within the processor in response to an instruction field. As opposed to a particular hard-wired interconnect, the dynamically variable interconnect may be modified to form an optimum interconnect for the particular algorithm being executed. Still further, the interconnect may be modified between several configurations during the execution of the algorithm, as often as each clock cycle. Because an instruction field is used to directly specify the configuration of the interconnect during execution of that instruction, control over the interconnect is afforded to the programmer writing the code which implements a particular algorithm.

Processor having a bus interconnect which is dynamically reconfigurable

A microprocessor including an instruction decode unit configured to detect a DSP call instruction is provided. The DSP call instruction is indicative of a call to a subroutine which performs a DSP function. Detected DSP call instructions are routed to a DSP which executes a routine performing the corresponding function. Subsequent to the DSP completing execution of the routine, the microprocessor continues execution at the instruction subsequent to the DSP call instruction. If a DSP is not included in the computer system, the DSP call instruction is executed in a manner similar to a subroutine call instruction. The microprocessor subsequently executes a corresponding routine which performs the DSP function.

Microprocessor configured to detect a DSP call instruction and to direct

A high speed adder suitable for incorporation into electronic digital processing circuits includes at least one first independent adder assuming a carry in of zero (0); at least one second independent adder assuming a carry in of one (1); carry prediction logic circuitry for producing carries for the first and second independent adders, which carry prediction logic circuitry is operable simultaneously with the first and second independent adders; and a final mux for producing a correct result based upon outputs received from the first and second independent adders and the carry prediction logic circuitry.

High speed mixed radix adder

A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent. If the result has a zero or negative exponent, the result is directed through the second arithmetic unit a second time so that the result is denormalized. The denormalized result is then output.

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Austin, TX, United States of America

Thomas W Lynch