Freescale Semiconductor,inc.

Other

Motorola Corporation

Thomas W Liston

Jianan Yang

Mark W Jetton

James David Burnett

Perry H Pelley

Brad John Garni

Shahnaz P Chowdhury-Nagle

Ravindraraj Ramaraju

Amit Gupta

Andrew Christopher Russell

George P Hoekstra

James B Eifert

Bradley J Garni

Jehoda Refaeli

Lawrence F Childs

Lawrence N Herr

Glenn E Starnes

Ashish Sharma

Olga R Lu

Huy Van V Pham

Huy Van Pham

In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.

Memory column drowsy control

A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.

Bypass system and method that mimics clock to data memory read timing

A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.

Semiconductor device with single-event latch-up prevention circuitry

In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).

Memory with word level power gating

A sensor circuit performs a method for sensing on-chip characteristics. The method includes generating a first voltage using a drive current through a first set of transistors that are operating in saturation mode and generating a second voltage using subthreshold leakage current from a second set of transistors that are in subthreshold mode. The method further includes comparing the second voltage to the first voltage to sense an on-chip characteristic. The sensed on-chip characteristic can be temperature and/or gate length variation.

Method and apparatus for sensing on-chip characteristics

A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation.

System and method for soft error detection in memory devices

A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

Single event latch-up prevention techniques for a semiconductor device

A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.

Dual port memory device

A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Memory with level shifting word line driver and method thereof

A circuit has a storing portion, a write portion and a read portion. In one embodiment, read portion has a transistor which has a substantially thinner gate oxide than the transistors in the storing portion and the transistors in the write portion. In an alternate embodiment, circuit has a plurality of read ports. In an alternate embodiment, selecting the optimal gate oxide thickness for the transistors in circuit allows the trade-off between transistor switching speed and gate leakage current to be optimized to produce a circuit having a fast enough read access time and a low enough standby power.

Circuit for storing information in an integrated circuit and method therefor

A method and apparatus for soft defect detection in a memory is disclosed. Bit lines are conditioned to predetermined voltages which ensure that, upon activation of the corresponding word line, all the storage transistors within the corresponding bit cells (at the intersection of the bit lines and the word line) are electrically conductive. A change in state of the bit cell in response to activation of the corresponding word line indicates the presence of a soft defect. An evaluator coupled to the memory may be used to identify defective memories by comparing the results of the testing to determine if any bit cells changed states. In one embodiment, the conditioning of the bit lines includes charging a bit line to a first predetermined voltage and its corresponding complementary bit line to a second predetermined voltage and then connecting the bit line and complementary bit line together to equalize the voltages.

Growing community of inventors

Austin, TX, United States of America

Thomas W Liston