Hewlett-packard Development Company, L.p.

Thomas W Grieff

Robert C Elliott

Greg John Pellegrino

James R Reif

Albert H Chang

Joseph Foster

Michael Lawrence Sabotta

Purna C Murthy

Systems and methodologies associated with providing additional functionality to a conventional SAS expander are described. One exemplary SAS expander embodiment includes logic for selectively performing source identifier checking for frames received at the SAS expander. The logic may also facilitate selectively performing explicit route checking for frames received at the SAS expander. In one example, the logic may also facilitate selectively providing VLAN-like services to devices connected to the SAS expander.

SAS expander

A host bus adapter for interconnecting a computer system to a storage area network has an embedded processor for processing frames. When frames are received by the processor, it inspects frames for encapsulated write requests and, if encapsulated write request frames are found, de-encapsulates the write request and forwards the write request to a target node of the write request.

System, machine, and method for maintenance of mirrored datasets through surrogate writes during storage-area networks transients

A system includes plural storage subsystems each having a controller and an expander to couple to storage devices. The controller accesses the storage devices through the expander, and the expander has interfaces for coupling to the storage devices. The system further includes an intercontroller link to connect expanders in two storage subsystems to enable the controller in one of the storage subsystems to communicate with the controller in another one of the storage subsystems through the expanders and the intercontroller link.

System having storage subsystems and a link coupling the storage subsystems

A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is implemented as a memory module for storing identifying information associated with commands received from multiple host devices, and a free pointers queue is maintained to track slots available in the outstanding request table. A command tracker state machine decodes incoming requests from hosts, monitors the execution by these commands by the ATA device, and updates the memory module to reflect completion of commands. Also disclosed is a storage system including an adapter of the present invention and ATA storage devices.

System and method for providing multi-initiator capability to an ATA drive

A system and method is disclosed for debugging of a hardware board that includes a processor with only a single level of interrupts that are either all enabled or all disabled. The processor does not implement nonmaskable interrupts. The processor on the board contains a machine check exception (MCP) input line that permits implementation of a nonmaskable pseudo-interrupt for debugging of the hardware board. The nonmaskable pseudo-interrupt informs the processor of a debug request even when all device interrupts in the interrupt processor are disabled. A processor-to-bus bridge connected to the processor on the hardware board contains a critical interrupt register. Test equipment connected to the processor-to-bus bridge sets a bit in the critical interrupt register for requesting the nonmaskable pseudo-interrupt, the processor-to-bus bridge reading the bit in the critical interrupt register to determine whether a nonmaskable pseudo interrupt debug request has occurred. The processor-to-bus bridge asserts the MCP input line of the processor after determining that the test equipment has requested the nonmaskable pseudo-interrupt. The processor then executes handler software that communicates with the test equipment to debug the hardware board.

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Pinehurst, TX, United States of America

Thomas W Grieff