Other

Digital Equipment Corporation

Thomas W Eggers

Richard A Warren

Stephen J Shaffer

William D Strecker

To prevent simultaneous usage of selected data signal groups in a data processing system, techniques are described to restrict such usage. First, with each location capable of storing a data signal group, a register cell can be assigned either in the main memory or in the cache memory units. When a data processing unit requests the data signal group, the register cell associated with each location in which the requested data signal group is stored has a control signal stored therein, and the control signal prohibits usage by another data processing unit. At the end of the activity, the requesting data processing unit removes the register cell control signal from all the locations storing the requested data signal group and the data signal group is then available to any requesting data processing unit. For groups of data signal groups, a file header can contain a control signal in a pre-selected location that identifies to the requesting processing unit that when the signal control is present, the file is unavailable for manipulation. In addition, the presence of the file protect control signal causes the data processing unit to execute a sub-routine, periodically interrogating the file header data signal group stored in the cache memory unit until the file protect signal is removed. After removal of the file protect signal, the execution of the program instruction sequence can continue. The file protect signal is stored in the file header signal group location when the first data processing unit requests access to the file. Using the file protect signal the related cache memory unit addressing sub-routine, activity involving the system bus can be minimized.

Apparatus and method for prohibiting access in a multi-cache data

In a data processing system in which a plurality of data processing units, as well as the main memory unit, are coupled to a system bus, the utilization of the system bus can be increased to such an extent that each of a plurality of cache memory units coupled to the system bus can have a plurality of data processing units coupled thereto. The system bus utilization is increased by dividing the system bus access operation into a plurality of sub-operations and by providing a defined cyclic sequence for the cache memory units to have access to the system bus. The system bus is divided into a plurality of sub-bus units to handle separate functions of data transfer. The main memory unit has apparatus for efficient execution of the write-modify-read operation. In addition, the cache memory units can be divided in a plurality of sub-units and the access to the system bus arranged in terms of cyclic access of the cache memory subunits.

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Littleton, MA, United States of America

Thomas W Eggers