International Business Machines Corporation

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Chartered Semiconductor Manufacturing Ltd (corporation)

Infineon Technologies North America Corp.

Other

Globalfoundries Inc.

Infineon Ag

Thomas W Dyer

Haining S Yang

Sunfei Fang

Jack Allan Mandelman

Zhijiong Luo

Andrew Herbert Simon

James J Toomey

Xiangdong Chen

Stephen Edward Greco

Jiang Yan

Bruce Bennett Doris

Huilong Zhu

Carl John Radens

Keith Kwong Hon Wong

Ronald G Filippi

Griselda Bonilla

Junjing Bao

Naftali Eliahu Lustig

James A Culp

Samuel S Choi

Jin-Ping Han

Matthew S Angyal

Tze-man Ko

Chih-Chao Yang

Dominic Joseph Schepis

Henry K Utomo

Rajendran Krishnasamy

Rajeev Malik

Junedong Lee

Jun Jung Kim

Daniel C Edelstein

Ramachandra Divakaruni

Herbert Lei Ho

Ravikumar Ramachandran

Anna Wanda Topol

David Robert Medeiros

Rama Divakaruni

Yiheng Xu

Stephan Kudelka

Scott David Halle

Yong Meng Lee

Kenneth T Settlemyer, Jr

Wei-Tsu Tseng

Shaoning Yao

Kyoung Woo Lee

Jong Ho Yang

Ja Hum Ku

Kenneth Settlemyer

Oleg Gluschenkov

Judson Robert Holt

Geng Wang

Michael Patrick Chudzik

Matthew Earl Colburn

Wai-Kin Li

Laertis Economikos

Eduard Albert Cartier

Jochen C Beintner

Michael P Belyansky

Chun-Yung Sung

Ravi Mahendra Todi

Werner A Rausch

Jin Ping Liu

Hiroyuki Akatsu

Naim Moumen

Venkatachalam C Jaiprakash

Chong Sup Chang

Alvin Wayne Strong

Siddhartha Panda

Min-Chul Sun

Sang-Jine Park

Min-ho Lee

Mahender Kumar

Chung Woh Lai

Yaocheng Liu

Johnny Widodo

Andreas Knorr

Ja-Hum Ku

William C Wille

Taehoon Lee

Giuseppe La Rosa

Seung-Man Choi

Hyung-rae Lee

Ernst H Demm

Jun-jung Kim

O-sung Kwon

JunJung Kim

Venkatachajam C Jaiprakash

Norbert Arnod

Venkatachaiam C Jaiprakash

Hanako Henry

Jinhong Li

A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Selective local metal cap layer formation for improved electromigration behavior

Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.

An integrated circuit structure provides at least one metal-insulator-metal (MIM) capacitor and a moat isolation structure wherein the number of processes required is substantially minimized and the formation of the MIM capacitor and the moat isolation structure effectively decouple while the number of processes common to the moat isolation structure and the MIM capacitor are maximized. Additional required processes are non-critical and tolerant of overlay positioning error.

Deep trench MIM capacitor and moat isolation with epitaxial semiconductor wafer scheme

A test layout structure including a first series of parallel metal lines in a first level, and a first series of contact structures in a second level, the second level being positioned above the first level, the first series of contact structures being positioned at known increments, where the increments are in a direction perpendicular to a length of the first series of parallel metal lines, and where one or more of the first series of contact structures is in electrical contact with one or more of the first series of parallel metal lines.

Measuring metal line spacing in semiconductor devices

A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

Doping of copper wiring structures in back end of line processing

A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.

Semiconductor device processing with reduced wiring puddle formation

The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.

CMOS devices with stressed channel regions, and methods for fabricating the same

Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Method of forming a planar field effect transistor structure with recesses for epitaxially deposited source/drain regions

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Pleasant Valley, NY, United States of America

Thomas W Dyer