Silicon Video, Inc.

Photon Vision Systems, Inc.

Panavision Imaging LLC

Thomas Vogelsong

Jeffrey Jon Zarnowski

Michael Joyner

Matthew A Pace

Matthew Pace

A bus system and an imager for transferring signals from a plurality of signal streams to an output includes a plurality of signal buses in parallel and a control system. The control system multiplexes the signals from two or more of the plurality of signal streams onto two or more of the plurality of signal buses and allows the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to the output. A method for transferring signals includes multiplexing signals on to two or more of a plurality of signal buses and allowing the signals to substantially charge each of the two or more of the plurality of signal buses before demultiplexing the signals to an output.

Video bus for high speed multi-resolution imagers and method thereof

An analog video bus architecture that utilizes the column parallel nature of CMOS imagers and more specifically Active Column Sensors, that eliminates the need for multi-port imagers, by increasing the useable bandwidth of single port imagers. An adaptation of this invention allows for either binning or interpolation of pixel information for increased or decreased resolution along the columns and more specifically for ACS imagers binning or interpolation along the rows. In this bus, the single video bus is replaced by multiple video buses and instead of selecting only one column for reading multiple columns are also pre-selected in-order to pre-charge the video bus. The video buses are then de-multiplexed back on to one port at the desired element rate. This architecture utilizes the column oriented video bus of CMOS imagers. It divides the large video bus capacitance by the number of video buses used. In addition, it allows multiple pixel time constants to precharge the video bus. The best commercially available imager designs now claim 40 MHz per analog port and suffer from reduced signal to noise ratios. To overcome this fundamental bandwidth limitation, imager designs in the past have had to increase the number of video ports per imager to achieve high frame rates. Multiple ports per imager breaks the focal plane into segments that are typically reassembled via post processing in a host computer. The other problem with multiple ports is each segment of the imager will have its own offsets and resultant Fixed Pattern Noise (FPN). PVS-Bus&trade; eliminates the objectionable segmentation and simplifies high-speed system design. Also, by utilizing the column parallel nature of CMOS video buses a method and improved method of using the PVS-Bus of binning and interpolation is described which results in increased frame rate, and for decreased or increased resolution.

Video bus for high speed multi-resolution imagers

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Jamesville, NY, United States of America

Thomas Vogelsong