Broadcom Corporation

Seagate Technology Incorporated

Avago Technologies International Sales Pte. Limited

Thomas V Souvignier

Gregory Lee Silvus

William G Bliss

Cenk Argon

Andrei Vityaev

Richard Martin Born

John P Mead

Peter Igorevich Vasiliev

Ahmad Darabiha

Chungming Tu

Yingquan Wu

Nan-Hsiung Yeh

Purnima Naganathan

Purmina Naganathan

An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.

Methods and systems for transcoder, FEC and interleaver optimization

Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices. A means is presented by which a number of blocks of information can be organized, with a degree of ECC provided thereto, and transmitted via a signal into a communication channel. In some instances, the communication channel is coupled to a storage media as in the context of an HDD, and information is written to and read from the storage media via this communication channel (e.g., 'read channel'). This means is particularly well suited to applications that provide large amounts of data via any one transmission (e.g., DVR/PVR (Digital/Personal Video Recorder)). A redundant block is generated using the information of each of a number of information blocks thereby provided extra ECC on a large portion of data, and that redundant block also undergoes ECC encoding.

Super block error correction code (ECC) adaptable to communication systems including hard disk drives (HDDs) and other memory storage devices

A scheme in which a first decoder provides first decoding of a signal read from a disk. A second decoder, coupled to an output of the first decoder, combines with the first decoder to provide iterative decoding to recover data stored on the disk when in an iterative mode of operation. However, when in a non-iterative mode of operation, the output of the first decoder is coupled to an error correction code module to apply error correction code (ECC) to the output of the first decoder to recover data stored on the disk by non-iterative decoding.

Use of ECC with iterative decoding for iterative and non-iterative decoding in a read channel for a disk drive

Timing recovery optimization using disk clock. A novel means is presented to perform and provide control of the sampling frequency of a signal that is read from a disk within a hard disk drive (HDD). Two separate, yet somewhat cooperating control loops are employed to provide feedback control of the sampling frequency of the signal that is read from disk. A timing recovery loop and a disk clock loop operate in conjunction with one another according to some desired manner (which can be predetermined or adaptive) to ensure that the sampling of the signal is performed to a very accurate degree. In one implementation, the timing recovery loop governs the sampling rate until the disk clock loop has locked, from which time either the disk clock loop govern the sampling or some combination of the signals provided from the two loops govern the sampling.

Timing recovery optimization using disk clock

A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) correction module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Disk clock system with up-sampler to generate frequency offset

Joint decoding of ISI (Inter-Symbol Interference) channel and modulation codes. A single, combined ISI and modulation decoding module is operable to process a signal received from an ISI communication channel and directly to generate a soft estimate of information encoded therein. A single module employs a decoding transfer function that is substantially matched to the communication channel that introduces the ISI and the modulation encoding performed on the information before being launched into the ISI communication channel. Such operations and functionality are adaptable to a variety of modulation coding systems that are tailored to deal with communication systems that introduce ISI. Moreover, such operations and functionality are extendable to communication systems employing an error correction code (ECC) such as Reed-Solomon (RS) coding as well as ECCs of an iterative nature such as LDPC (Low Density Parity Check) coding, turbo coding, and/or turbo trellis code modulation (TTCM) coding.

Joint decoding of ISI (inter-symbol interference) channel and modulation codes

An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Interleaver with linear feedback shift register

A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) collection module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

An apparatus, system and method in which a plurality of interleavers are utilized with the outputs of the interleavers being combined to generate a single combined output are provided. In a preferred embodiment, at least two of the plurality of interleavers are of a different type. For example, in one exemplary embodiment, a first interleaver is an S-random interleaver with a second interleaver being one of an algebraic, convolutional, helical, pseudo random, or other type of interleaver. Combinational logic receives the output from each of the plurality of interleavers and combines the outputs to generate one combined output having a permuted order. By combining the outputs from a plurality of interleavers, a greater amount of randomness in the input data may be obtained as opposed to that of the known single interleaver systems. In addition, by using a plurality of interleavers of different types, the limits of each individual type of interleaver may be relaxed in order to obtain a greater versatility of interleaver operation.

Method and apparatus for combining output of different type interleavers based on an input data sequence to obtain a combined output

A communications channel is provided, which includes a receive path having an iterative decoder and an ECC decoder. The iterative decoder has a soft channel detector with a soft output. The ECC decoder is coupled to decode bits produced from soft information received from the soft output and operates on the bits in a bit order that is the same as that on the soft output.

Iterative detector with ECC in channel domain

A method or apparatus that can form and test a data block variant by flipping a selected potentially bad bit that is consecutive with 1 or 2 sequences of several potentially good bits of a received block. The variant correctability test is optionally repeated several times before receiving another data block, in the event of ECC failures, each repetition using a different block variant.

Soft-decision decoding using selective bit flipping

Low complexity pseudo-random interleaver

A sequence generator is configured to be re-initialized to a value selected derived from a candidate group that is derived from a predetermined value. If and when the re-initializing is performed, it is fully performed within about one clock cycle of setting the sequence generator to the predetermined value. The sequence generator is optionally initialized by a local processor to which it is operatively coupled, after which the processor receives one sequence value each cycle.

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Longmont, CO, United States of America

Thomas V Souvignier