Infineon Technologies Ag

Thomas Stoek

Dirk Ahlers

Michael Stadler

Stefan Macheiner

Chee Voon Tan

Daniel Schleisser

Chau Fatt Chiang

Swee Kah Lee

Frank Daeche

Chii Shang Hong

Josef Maerz

Chiew Li Tai

Edmund Sales Cabatbat

Mohd Hasrul Zulkifli

Gilles Delarozee

Christopher Spielman

Ivan Nikitin

Teck Sim Lee

Christian Stuempfl

Chooi Mei Chong

Lee Shuang Wang

Sanjay Kumar Murugan

Ke Yan Tean

Jayaganasan Narayanasamy

Fabian Schnoy

Amirul Afiq Hud

Jagen Krishnan

Michael Niendorf

Oliver Markus Kreiter

Elvis Keli

Mei Fen Hiew

Angel Enverga

Ludwig Busch

Kean Ming Koe

Christian Feuerbaum

Tian See Hoe

Bernhard Stiller

Syahir Abd Hamid

Mian Mian Lam

Wei Hing Tan

An integrated circuit package includes a leadframe with a die pad and a lead. A semiconductor die is attached to a top surface of the die pad. A clip has a lead contact area with a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. A portion of the surface pattern is attached to a top surface of a terminal pad of the lead. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The die contact area of the clip is attached to a top contact on the semiconductor die. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead.

Leadframe package with adjustable clip

A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness.

Semiconductor package, metal sheet for use in a semiconductor package, and method for producing a semiconductor package

A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.

Molded semiconductor package having a negative standoff

A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste that reflowed to form the soldered joint. Corresponding methods of production are also described.

Semiconductor device having a metal clip with a solder volume balancing reservoir

A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/&#x2212;30 &#x3bc;m at the first side of the power module.

Power semiconductor module for PCB embedding, power electronic assembly having a power module embedded in a PCB, and corresponding methods of production

A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

Molded semiconductor module having a mold step for increasing creepage distance

A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.

Metal clip with solder volume balancing reservoir

A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.

Double-sided cooled molded semiconductor package

A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.

Semiconductor arrangement, laminated semiconductor arrangement and method for fabricating a semiconductor arrangement

A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.

Semiconductor package having leads with a negative standoff

An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.

Multi-branch terminal for integrated circuit (IC) package

A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.

Molded semiconductor package with double-sided cooling

A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating.

Selective plating of semiconductor package leads

A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.

Growing community of inventors

Buxtehude, Germany

Thomas Stoek