Infineon Technologies Ag

Qimonda Ag

Thomas Schuster

Jürgen Faul

Jürgen Amon

Thomas Ruder

Johann Harter

Ulrike Gruening

Matthias Goldbach

Johann Alsmeier

Frank Jakubowski

Juergen Faul

Dirk Offenberg

Martin Popp

Albrecht Kieslich

Jens Hahn

Rudolf Strasser

Wilhelm Kegel

Dirk T&ouml;bben

Ralf Müller

One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove. The lower portion of said gate groove is filled with polysilicon whereas the upper portion of said gate groove is filled with a metal or a metal compound thereby forming a gate electrode disposed along said channel region. Said gate electrode controls an electrical current flowing between said first and second source/drain regions.

Transistor, memory cell, memory cell array and method of forming a memory cell array

A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.

Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure

Provided is an integrated circuit including a transistor with a gate electrode. The gate electrode includes a polysilicon layer in contact with a gate dielectric layer separating the gate electrode and a semiconductor substrate that comprises an active region of the transistor. The gate electrode includes sidewall structures extending along lower portions of opposing sidewalls of the polysilicon layer, the lower portion being oriented to the semiconductor substrate. The gate electrode also includes a barrier layer. A first section of the barrier layer extends along an upper portion of the sidewall of the polysilicon layer, the upper portion being adjacent to the lower portion and facing away from the semiconductor substrate.

Field-effect transistor structures with gate electrodes with a metal layer

Provided is a method for fabricating gate electrode structures each having at least one individual polysilicon layer and a metal layer. A polysilicon layer is provided and patterned prior to the application of the gate metal. Trenches between the resulting gate structures are filled, and the polysilicon is drawn back to below the top edge of the fillings. The relief formed from the fillings and the polysilicon which has been caused to recede forms a shape which is used to pattern the gate metal without a lithographic step. The provision of a gate sacrificial layer, which is patterned together with the polysilicon layer, makes it possible to form contact structures from a contact metal prior to the application of the gate metal.

Method for fabricating field-effect transistor structures with gate electrodes with a metal layer

A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

Method for fabricating a semiconductor structure

Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.

The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS, GS, GS, GS) on a semiconductor substrate (), having the following steps: application of the gate stacks (GS, GS, GS, GS) to a gate dielectric () above the semiconductor substrate (); formation of a sidewall oxide () on sidewalls of the gate stacks (GS, GS, GS, GS); application and patterning of a mask () on the semiconductor structure; and implantation of a contact doping () in a self-aligned manner with respect to the sidewall oxide () of the gate stacks (GS, GS) in regions not covered by the mask ().

A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

Field effect transistor and fabrication method

A method for controlling temperature of a semiconductor wafer in a process chamber includes heating the chamber from a starting temperature to a stabilizing temperature at a heating rate of approximately 12 degrees Celsius per second and maintaining the chamber at the stabilizing temperature for a selected stabilization period. The chamber is then heated from the stabilizing temperature to a process temperature at a heating rate of approximately 10 degrees Celsius per second. This process temperature is maintained for a selected processing period. After the period, the chamber is cooled to an exit temperature at a selected low cooling rate.

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Dresden, Germany

Thomas Schuster