Infineon Technologies Ag

Siemens Aktiengesellschaft

Infineon Technologies Richmond, LP

Texas Instruments Corporation

Qimonda Ag

Infineon Technologies LLC

Thomas Schulz

Lothar Risch

Christian Pacha

Wolfgang Rösner

Christian Cornelius Russ

Franz Hofmann

Harald Gossner

Erhard Landgraf

Ralf Peter Brederlow

Michael Specht

Richard Johannes Luyken

Jessica Hartwich

Sergei Postnikov

Gerhard Enders

Dietrich Widmann

Gerhard Knoblinger

Wolfgang R&ouml;sner

Hongfa Luan

Johannes Kretz

Thomas Nirschl

Franz Kreupl

Ronald Kakoschke

Wolfgang Roesner

Hong-Jyh Li

Doris Schmitt-Landsiedel

Jens Schneider

Klaus Schruefer

Juergen Holz

Nirmal Chaudhary

Wolfgang Hönlein

Koen Van Der Zanden

Andrew Graham

Thomas Aeugle

Hans-Joachim Barth

Martin Franosch

Herbert Schäfer

Weize W Xiong

Wolfgang Rosner

Klaus Von Arnim

Chris Stapelmann

Craig Henry Huffman

Johannes Luyken

Ties Ramcke

Thomas Äugle

Ralf Gottsche

Thomas &Auml;ugle

Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.

Semiconductor devices and methods of manufacture thereof

One embodiment provides an integrated circuit including a first non-planar structure and a waveguide configured to provide electromagnetic waves to the first non-planar structure. The first non-planar structure provides a first signal in response to at least some of the electromagnetic waves.

Integrated circuit including non-planar structure and waveguide

Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.

Feature patterning methods and structures thereof

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor

One or more embodiments relate to a floating gate memory device, comprising: a substrate; a floating gate disposed over the substrate; and a control gate substantially laterally surrounding at least a portion of the floating gate.

Floating gate memory device with at least partially surrounding control gate

An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD) in comparison with other transistors (T) on the same integrated circuit arrangement (). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D, S) of the tunnel field effect transistor.

Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin.

In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.

Method for producing a thyristor

In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.

An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.

Integrated circuit arrangement with capacitor and fabrication method

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Heverlee, Belgium

Thomas Schulz