Infineon Technologies Ag

Thomas Schafbauer

Hans-Joachim Barth

Erdem Kaltalioglu

Kai Esmark

Sebastian Schmidt

Martin Streibl

Uwe Kerst

Tobias Mono

Martin Wendel

Yayi Wei

Hang Yip Liu

Petra Felsner

Paul Wensley

Chuan Lin

Hang-Yip Liu

Andreas Von Ehrenwall

Philipp Riess

A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.

Structure and method for placement, sizing and shaping of dummy structures

A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.

Capacitor and method of manufacturing a capacitor

Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with methods of fabricating such semiconductor devices. The interconnections comprise a via and a metal layer.

A method for electrically determining in a semiconductor wafer the location of edges of a well that underlies an insulating layer that includes forming in the wafer before forming of the well and the insulating layer a plurality of conductive stripes will that pass under the future insulating layer and extend to varying distances under the insulating layer so as to include stripes that will penetrate an edge to be located so as to form a low resistance connection thereto and stripes that will fall short of an edge to be located. From the stripes of minimum penetration that make low resistance can be determined the location of the well edges.

Structure for determining edges of regions in a semiconductor wafer

A method of forming a semiconductor structure (see e.g., FIG. ) includes forming a silicon (e.g., polysilicon) layer . The silicon layer is patterned and etched so that at least one sidewall is exposed. An oxygen bearing species (e.g., O ) is then implanted into the sidewall of the silicon layer . In the preferred embodiment, the oxygen bearing species is implanted at an acute angle relative to the plane of the silicon layer

Semiconductor device formed with an oxygen implant step

A method (see e.g., FIG. ) of fabricating a semiconductor device includes forming a trench in a semiconductor body . A dielectric layer is formed within the trench . Dielectric layer lines the sidewall and, possibly, the bottom portions of the trench in a manner where the thickness of the dielectric at the sidewall is greater than the thickness of the dielectric at the bottom. A dopant can then be implanted into the semiconductor body beneath the trench.

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Paris, France

Thomas Schafbauer