Silicon Laboratories Inc.

Cirrus Logic Inc.

Thomas Saroshan David

Alan Lee Westwick

Kenneth Wilson Fernald

Douglas S Piasecki

Bradley Martin

Randall Kent Sears

Timothy Thomas Rueger

Sebastian Ahmed

Paul Zavalney

Stefan N Mastovich

Phillip Matthews

Daniel J Cooley

Jia-Hau Liu

Wasim Quddus

Douglas D Gephardt

Michael Johnson

James David Barnette

Scott Thomas Haban

Gregory Allen North

Paul Highley

James Dub Austin

Marius Grannaes

Adrianus Josephus Bink

Aslam A Rafi

Linxiao Shen

Joshua Jay Norem

Brian Christopher Kircher

Aslam Rafi

Methods of performing updates to a software image that is disposed in a read only memory or a one time programmable memory device are disclosed. The method includes causing an ECC error at the beginning of a function that has been modified. This ECC error causes an exception. The exception handler determines the address where the ECC error was detected was located and searches a dictionary. This dictionary contains entries that each have an original address in the ROM or OTP Memory and the patch address in a nonvolatile writable memory. The exception handler then causes the processing unit to jump to the patch address, where a modified function is located.

ROM/OTP patching using ECC/parity manipulation

An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

External nonvolatile memory with additional functionality

An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

Interface between processing unit and an external nonvolatile memory

A flip-flop including a scan enable input for receiving a scan enable signal, a clock input for receiving a clock signal, input select circuitry that is configured to select between a data input and a scan input based on a state of the scan enable signal for providing a selected input, latching circuitry that is configured to latch the selected input to a preliminary output node in response to transitions of the clock signal, and output select circuitry that is configured to provide a state of the preliminary output node to a selected one of a scan output and a data output based on a state of the scan enable signal. The flip-flop may be implemented using fast yet leaky transistors. The data output may be disabled to prevent toggling other circuitry when scanning into or out of a memory for data retention.

Flip-flop with input and output select and output masking that enables low power scan for retention

In one example, an apparatus includes: a radio frequency (RF) receiver to receive an RF signal; a media access control (MAC) circuit to receive data and output MAC-processed data according to a clock signal that is phase delayed with respect to a source clock signal when the RF receiver is active; and an interference mitigation circuit to receive the MAC-processed data and provide the MAC-processed data to a physical circuit resynchronized to the source clock signal.

System, apparatus and method for mitigating digital interference within radio frequency circuitry

A data synchronizer including an input stage, a driver stage, and a keeper stage. The input stage latches input data to a data node in response to a first clock signal transition. The driver stage has an input coupled to the data node and has an output coupled to a gain node. The keeper stage latches data asserted on the gain node back to the input stage to maintain data on the data node in response to a second transition of the clock signal. The driver stage has an increased drive strength and a reduced loading capacitance to increase the gain-bandwidth product of the latch loop to reduce metastability. A flip-flop may be configured with input and output latches each including driver stages having increased drive strength and reduced loading capacitance to increase the gain-bandwidth product of each of the latch loops to reduce metastability.

High-speed synchronizer with lower metastability failure rate

A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.

Configurable clock buffer for multiple operating modes

A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

State retention circuit that retains data storage element state during power reduction mode

An apparatus includes a communication circuit coupled to a communication link, a wakeup detector, and a power control circuit. The communication circuit has a first state and a second state. The power consumption of the communication circuit is lower in the second state than in the first state. The wakeup detector is coupled to the communication link. The wakeup detector generates a wakeup signal to cause the communication circuit to make a transition from the second state to the first state in response to an occurrence of an event on the communication link. The power control circuit selectively supplies power to the communication circuit in response to the wakeup signal.

Low-power communication apparatus with wakeup detection and associated methods

A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

ECC memory controller to detect dangling pointers

A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.

ECC memory controller supporting secure and non-secure regions

A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.

Dynamic containerized system memory protection for low-energy MCUs

A system for communicating information includes one device that communicates information via a communication link. The system also includes a second device to communicate information via the communication link. The second device includes a receiver to receive information from the communication link. The second device also includes an oscillator that provides at least one timing signal to the receiver. The oscillator is disabled when the communication link is in an idle state. The oscillator is enabled when the communication link is in a non-idle state.

Communication apparatus having an oscillator that is disabled based on idle state detection of a communication link and associated methods

An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.

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Austin, TX, United States of America

Thomas Saroshan David