Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Thomas Santa

Thoralf Kautzsch

Mirko Vogt

Maik Stegemann

Heiko Froehlich

Roberto Nonis

Peter Thurner

Markus Burian

Nicola Da Dalt

Bernd Zimek

George Efthivoulidis

Tony Gschier

Andrea Bandiziol

Andrea Tollot

A radar monolithic microwave integrated circuit (MMIC) includes a trigger encoder configured to receive a clock signal comprising a plurality of clock pulses having a fixed amplitude and a trigger signal configured to indicate trigger events. The trigger encoder is configured to encode the trigger signal into the clock signal to generate a distributed clock signal by skipping at least one clock pulse of the plurality of clock pulses to indicate a trigger event. The radar MMIC is configured to output the distributed clock signal having the at least one clock pulse skipped to indicate the trigger event. The radar MMIC is configured to receive the distributed clock signal as a received distributed clock signal. The radar MMIC further includes a radar operation controller configured to detect the trigger event based on the received distributed clock signal and initiate a radar operation based on detecting the trigger event.

Trigger signaling through a clock signal in cascading radar systems

A circuit includes: a first load circuit and a second load circuit coupled in parallel between a first node and a reference voltage node, where the first load circuit and the second load circuit are configured to receive a first input signal and a second input signal, respectively; a first pass device and a first switch coupled in series between a voltage supply node and the first node; a second pass device and a second switch coupled in series between the voltage supply node and the first node; and an amplifier, where a first input terminal and a second input terminal of the amplifier are configured to be coupled to a reference input voltage and the first node, respectively, where an output terminal of the amplifier is coupled to a first control terminal of the first pass device and a second control terminal of the second pass device.

Voltage regulator and circuits with a voltage regulator

Representative implementations of devices and techniques provide non-linearity detection and mitigation for a phase interpolator of a controlled oscillator circuit, such as a PLL. A bit stream output of a phase detector of the oscillator circuit is segmented according to multiple phase positions of the phase interpolator, forming a bit stream for each of the multiple phase positions. Each bit stream of each phase position is analyzed, and phase position errors may be detected and mitigated based on the contents of the bit streams.

Detection and mitigation of non-linearity of phase interpolator

A method of forming a resonator by providing a first layer; forming a sacrificial layer on the first layer; forming a capping layer on the sacrificial layer; forming at least one etching aperture in the capping layer; forming at least one additional aperture having a different size than the at least one etching aperture; forming a cavity and releasing a resonator structure within the cavity by removing the sacrificial layer by etching via the at least one etching aperture; sealing the at least one etching aperture; and forming a lining in the at least one additional aperture.

Method of forming a resonator

Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.

Phase interpolator

Embodiments relate to MEMS resonator structures and methods that enable application of a maximum available on-chip voltage. In an embodiment, a MEMS resonator comprises a connection between a ground potential and the gap electrode of the resonator. Embodiments also relate to manufacturing systems and methods that are less complex and enable production of MEMS resonators of reduced dimensions.

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Seeboden, Austria

Thomas Santa