Infineon Technologies Ag

Thomas Sailer

Jochen Oliver Schrattenecker

Oliver Frank

Michael Kropfitsch

Rainer Stuhlberger

Florian Starzer

Peter Bogner

Helmut Kollmann

Klemens Kordik

Guenter Haider

Bernhard Gstoettenbauer

Vincenzo Fiore

Georg Krebelder

Klaus Buchner

Michael Platzer

A method is disclosed use with a circuit device that includes a circuit having a predetermined voltage-current characteristic and a detector configured to detect a voltage-current relation of the circuit. The method includes using the detector to detect the voltage-current relation of the circuit, and indicating if the detected voltage-current relation differs from the predetermined voltage-current characteristic. A circuit device includes a circuit having a predetermined voltage-current characteristic, and a detector configured to detect a voltage-current relation of the circuit. The circuit device is configured to indicate if the detected voltage-current relation differs from the predetermined voltage-current characteristic.

Health monitoring of a circuit

A radar device comprises a test signal generator including a digital harmonic oscillator that generates a digital oscillator signal with a first spectral component; a first digital-to-analog-converter that generates an analog oscillator signal based on the digital oscillator signal. Furthermore, the radar device comprises at least one radar channel receiving the analog oscillator signal during one or more self-tests.

RF receiver with built-in test capabilities

A radar sensor includes a mixer configured to receive an radio frequency (RF) input signal to down-convert the RF input signal into a base-band or intermediate frequency (IF) band, an analog-to-digital converter (ADC), and a signal processing chain coupled between the mixer and the ADC. The radar sensor further includes an oscillator circuit that is configured to generate a test signal. The ADC is coupled to an output of the signal processing chain, and is configured to generate a digital signal by digitizing an output signal of the signal processing chain, the output signal being derived from the test signal. The radar sensor further includes a digital signal processing circuit coupled to the ADC downstream thereof, the digital signal processing circuit being configured to perform a spectral analysis on frequency values of the digital signal.

RF receiver with built-in self-test function

A radio frequency (RF) receive circuit is described herein. In accordance with one embodiment, the RF receive circuit includes a mixer configured to receive an RF input signal to down-convert the RF input signal into a base-band or intermediate frequency (IF) band, an analog-to-digital converter (ADC), and a signal processing chain coupled between the mixer and the ADC. The signal processing chain includes at least two circuit nodes. The RF receive circuit further includes an oscillator circuit that is configured to generate a test signal. The oscillator circuit is coupled to the signal processing chain and is configured to selectively feed the oscillator signal into one of the at least two circuit nodes.

A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.

Clock monitoring for sequential logic circuits

A detector for detecting a locked state and an out-of-lock state of a phase locked loop includes an out-of-lock detector circuit that receives a reference signal and an input signal representing a PLL oscillator signal. The out-of-lock detector detects an out-of-lock state of the PLL and generates an out-of-lock signal indicating whether an out-of-lock state is detected. The detector further includes a lock detector circuit that receives the reference signal and the input signal, detects a locked state of the PLL, and generates a lock signal indicating whether a locked state is detected. A logic circuit receives both the out-of-lock signal and the lock signal and combines both signals to obtain an output signal indicative of whether the PLL is in a locked state or an out-of-lock state.

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Zwettl a.d. Rodl, Austria

Thomas Sailer