Advanced Micro Devices Corporation

Neophotonics Corporation

Lightwave Microsystems Corporation

Fontecha, Ed

Quirke, David J.

Mcginnis, Brian

Seto, Sam

Long, Wilson

Ho, Calvin

Zhao, Liang

Tarter, Thomas S.

Thomas S Tarter

Calvin Ho

Nhon T Do

Anthony J Ticknor

Hao Xu

Ming Yan

Jane Lam

Jason Weaver

Liang Zhao

Shrikar Bhagath

Eric Tosaya

Paul J Sokolovsky

Charles Anderson

Wilson Long

Tom Ley

Peter D Ascanio

David James Quirke

Brian P McGinnis

Ed Fontecha

Sam Seto

Brian Mcginnis

David J Quirke

A linearized thermal and optical model of an optical integrated circuit can be used to temperature-stabilize one or more optical elements of the circuit using active temperature regulation. To stabilize a single optical element, a temperature sensor and a heater can be provided proximate to the grating. Thermal and optical coefficients can be then used to select an appropriate temperature set-point for the temperature controller that receives readings from the sensor and determines the power dissipated in the heater. Multiple optical elements can be stabilized individually, using the same process and lumping cross-heating factors together with other environmental factors. Alternatively, multiple AWG's can be stabilized using fewer sensors than optical elements, by stabilizing one of the optical elements in the same manner as in the case of a single optical elements, and determining power dissipated in the heaters of the remaining optical elements based on the linearized model.

Thermal control of optical components

An optical device with a non-rectilinearly shaped optical integrated circuit over a substantially flat portion of a riser, the riser also equipped with a relief structure that is in thermal contact with a stabilizing brace that is in turn connected to two portions of the non-rectilinearly shaped optical integrated circuit. The non-rectilinearly shaped optical integrated circuit exhibits reduced center wavelength drift.

Stable center wavelength performance in non-rectilinearly shaped optical integrated circuit chip

A linearized thermal and optical model of an optical integrated circuit can be used to temperature-stabilize one or more optical elements of the circuit using active temperature regulation. To stabilize a single optical element, such as an arrayed waveguide grating (AWG), a temperature sensor and a heater can be provided proximate to the grating. Thermal and optical coefficients can be then used to select an appropriate temperature set-point for the temperature controller that receives readings from the sensor and determines the power dissipated in the heater. Multiple AWG's can be stabilized individually, using the same process and lumping cross-heating factors together with other environmental factors. Alternatively, multiple AWG's can be stabilized using fewer sensors than AWG's, by stabilizing one of the AWG's in the same manner as in the case of a single AWG, and determining power dissipated in the heaters of the remaining AWG's based on the linearized model.

Systems and methods for an isothermal thin film heater are provided. The isothermal thin film heater mitigates temperature variations in an optical circuit, such as an arrayed-waveguide grating. The thin film heater comprises a conductive plate and at least one heating element trace coupled to the conductive plate for heating the optical circuit. The heating element trace(s) is arranged around a periphery portion of the conductive plate such that concentric arcs are formed by the heating element trace(s). A sensor for sensing the temperature of the thin film heater and/or the optical circuit can also be provided.

Isothermal thin film heater

A thermal test chip array and method of forming the same allows access to any test die in the array regardless of the size of the array. The thermal test chip arrangement has a plurality of thermal test chips arranged in an array, each thermal test chip having a heating circuit and a temperature-sensing circuit. A first set of conductive lines traverse unbroken across the entire array. The heating circuit of each thermal test chip is connected to some of the first set of conductive lines. These conductive lines provide power to the heating circuits of the thermal test chips. A second set of conductive lines traverse unbroken across the entire array with the temperature-sensing circuit of each thermal test chip being connected to some of the second set of conductive lines. Power is carried to the temperature sensing circuits of the thermal test chips by the second set of conductive lines.

Programming thermal test chip arrays

An intregrated circuit package, which has an intregrated circuit die thereto, is mounted to a system board. The ground trace of the system board is connected to the package, which has a pluality of ground leads on its surface. An electrically conductive epoxy is placed on the ground leads and adheres the package lid to the package board and ground the package lid. A heat sink is mounted to the package lid with an electrically conductive adhesive or electrically conductive slips that extend from a flange of the package lid to a flange of the heat sink to ground the heat sink.

Heat sink grounded to a grounded package lid

A test fixture and method of isolating an electrical contact of chip scale package for testing the electrical characteristics of the electrical contact has a base and an isolation plate. The isolation plate is configured to contact and ground all of the electrical contacts of the chip scale package under test, except for a selected subset of the electrical contacts. The isolation plate includes a hole that provides access to the selected subset of electrical contacts to allow a test probe access to the isolated electrical contact.

Chip scale electrical test fixture

An integrated circuit package test station supports an integrated circuit package under test in a vertical orientation thereby allowing simultaneous access to both sides of the package. Probe assemblies are utilized on both sides of the package to increase the accuracy, efficiency, and simplicity of performing electrical characterization of the IC package. The IC package holder as well as the probe assemblies are adjustably positioned to allow accurate and precise measurements of through-package electrical characteristics. To aid in positioning the test equipment, a dual-display image magnification system is used which provides images from both sides of the IC package simultaneously.

Method and apparatus for electrical characterization of an integrated circuit package using a vertical probe station

A lead cut and tape attach apparatus (10) for automatically cutting leads on one side of a semiconductor I.C. quad device and subsequently cutting and attaching a piece of tape over the gaps formed between the cut leads and for sequentially cutting the leads and attaching tape thereover on the remaining sides of the quad device includes a double-acting punch assembly (34) formed of an inner punch blade (58) and an outer punch (56). There is provided upper and lower cams (68, 78) for actuating the inner punch blade relative to the outer punch so that on a first downward stroke the inner punch blade is extended to cut the leads of the quad device. On a second downward stroke of the punch assembly, the inner punch blade is retracted and the outer punch cuts and attaches the tape.

Lead cut and tape attach apparatus

Growing community of inventors

San Jose, CA, United States of America

Thomas S Tarter