International Business Machines Corporation

Other

Siemens Aktiengesellschaft

Infineon Technologies Ag

Infineon Technologies North America Corp.

Qimonda Ag

Thomas S Rupp

Ulrike Gruening

Jeffrey P Gambino

Jack Allan Mandelman

Carl John Radens

David V Horak

Toshiharu Furukawa

Scott David Halle

Axel Christoph Brintzinger

Lawrence Alfred Clevenger

Ramachandra Divakaruni

Ravikumar Ramachandran

Chandrasekhar Narayan

Richard Anthony Conti

Viraj Yashawant Sardesai

Gerhard Mueller

Stephan Kudelka

Johann Alsmeier

Mary Elizabeth Weybright

Donna Rizzone Cote

Peter D Hoh

Alan C Thomas

Kenneth C Arndt

Franz X Zach

Greg Costrini

Rainer Florian Schnabel

Senthil K Srinivasan

Senthil Srinivasan

Yoichi Otani

Dave Dobuzinsky

A semiconductor device includes a substrate forming a trench, the trench including a storage node disposed within the trench. A wordline is disposed within the substrate and adjacent to a portion of the substrate. A vertically disposed transistor is included wherein the wordline functions as a gate, the storage node and a bitline function as one of a source and a drain such that when activated by the wordline the transistor conducts between the storage node and the bitline. The invention further includes a method of fabricating the semiconductor device with vertical transistors.

Vertical device formed adjacent to a wordline sidewall and method for semiconductor chips

In one aspect, the present invention discloses a transistor device (see e.g., FIG. ) that includes first and second source/drain regions and disposed in a semiconductor body and separated by a channel region A dielectric layer overlies the channel region and a gate electrode overlies the dielectric layer In the preferred embodiment, the gate electrode includes a polysilicon layer that extends a first lateral distance over the dielectric layer and a silicide layer that extends a second lateral distance over the first polysilicon layer. In this example, the first lateral distance is greater than the second lateral distance.

Semiconductor contact and method of forming the same

The present provides a method for tailoring silicon dioxide source and drain implants and, if desired, extension implants of different devices used on a semiconductor wafer in order to realize shallow junctions and minimize the region of overlap between the gate and source and drain regions and any extension implants. The method includes the steps of applying a mask over a first gate structure positioned on a semiconductor substrate, depositing a layer of a spacer material over the surface of the first gate structure and a second gate structure adjacent to the first gate structure, etching the spacer material so that a portion of the spacer material remains on the second gate sidewalls and a sidewall of the block out mask, implanting ions into the semiconductor substrate into a region defined between the spacer material on the block out mask and the second gate to form a source or drain region, and removing the spacer material and block out mask. If desired, a second etch can be performed on the spacer material to reduce spacer thickness, and second ions can be implanted into the semiconductor substrate into an implant region defined between the spacer material remaining after the second etch.

Disposable spacer technology for device tailoring

A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts are formed between first level bitlines in the array region and a first portion of the first contacts, while forming second contacts to a first metal layer from the gate structures and diffusion regions in the support region. Third contacts are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer from the first metal layer in the support region.

Locally folded split level bitline wiring

A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.

Manufacturing of cavity fuses on gate conductor level

A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C,F,, 20-80 sccm of CO, 2-30 sccm of O,and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

Method of forming wires on an integrated circuit chip

A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.

Embedded vertical DRAM cells and dual workfunction logic gates

A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffision region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.

Process of manufacturing a vertical dynamic random access memory device

In order to form a cavity for a fusible link in a semiconductor device, an etchable material is applied over and around a portion of the fusible link and the etchable material is coated with a protection layer. The access abutting the etchable material is formed through the protection layer. After the removal of the etchable material, the access is partially filled with a refilling material to thereby form the cavity.

Method for manufacturing fusible links in a semiconductor device

A method for patterning semiconductor components includes the steps of providing a substrate layer, the substrate layer having a dielectric layer formed thereon and a mask layer formed on the dielectric layer, the mask layer being selectively etchable relative to the dielectric layer, patterning the mask layer to form a first group of substantially parallel lines in the mask layer and patterning the dielectric layer to form rectangular holes therein down to the substrate layer. A semiconductor device in accordance with the invention is also included.

Contact and deep trench patterning

A word line is buried beside a vertical semiconductor device. The word line is embedded adjacent to the vertical semiconductor device such that the topography of the word line is substantially planar. The planar features of the buried word line allows further processing to performed over the word line and the vertical transistor. In another embodiment, the vertical semiconductor device is a transistor having a vertically oriented gate. The word line is buried beside the vertically oriented gate, such that the topography of the word line is substantially planar.

Semiconductor device with vertical transistor and buried word line

A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.

Vertical DRAM cell with wordline self-aligned to storage trench

A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface of the silicon substrate. One portion of the silicon dioxide layer is over a first isolated region and another portion of the silicon dioxide layer being over a second isolated region. An inorganic layer is formed over the silicon dioxide layer extending over the isolated regions of the silicon substrate. A first portion of the inorganic layer is over the first isolated regions and a second portion of the inorganic layer is over the second isolated regions. A photoresist layer is formed over the inorganic layer. The photoresist layer is patterned with a window over the first portion of the inorganic layer. The photoresist layer covers the second portion of the inorganic layer. The inorganic layer is patterned into an inorganic mask by bringing a etch into contact with the patterned photoresist layer to selectively remove the first portion of the inorganic layer an thereby expose an underlying portion of the surface of the silicon substrate while leaving the second portion of the inorganic layer. The inorganic mask is used to selectively remove exposed portions of the grown silicon dioxide. The inorganic mask is removed. A second layer of silicon dioxide is grown over the exposed underlying portion of the silicon substrate to a thickness different from the thickness of the first layer of silicon dioxide. The silicon dioxide layers are patterned into gate oxides for each of a corresponding one of the pair of MOSFETs.

Growing community of inventors

Stormville, NY, United States of America

Thomas S Rupp