International Business Machines Corporation

Thomas S Robinson

David Otto Lewis

William Frank Micka

Roy L Hoffman

William E Hammer

Eugene R Jones

John W Reed

Keith K Slack

Nyles N Heise

Mark Fernando Diez

Michael Alfred Goolsbey

James J Pertzborn

Istvan S Kiss

A field of scanned video pels is first broken up into cells representing small portions of characters to be recognized, according to a first set of logics. A second set of logics then recombines the cells into blocks containing individual characters separated from their neighbors.

Locating individual images in a field for recognition or the like

Control apparatus is responsive to CPU I/O commands for initiating chained I/O data transfers to cause virtual address translation (VAT) apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address in an I/O resolved address register reserved (unique) to the commanded I/O device connected to a shared I/O control unit and to repeat such an operation for each I/O device commanded by the CPU to do a data transfer and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into I/O resolved address registers shared for use by all of I/O devices whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit.

Control apparatus for virtual address translation unit

In a paged, virtual memory computer system an apparatus is provided for enabling I/O device adapters to request the CPU to allocate or resolve virtual pages into main storage pages as required for I/O data transfers. The I/O adapter provides the channel virtual address information specifying the requested page and channel function information which indicates whether the requested page is to be transferred from secondary storage into main storage or merely allocated as a page in main storage. The channel forms the virtual address information and the channel function information into a page request function event which is stored in an I/O event stack in main storage for retrieval and processing by the CPU.

Allocating and resolving next virtual pages for input/output

A monitor circuit for overseeing input/output activity in a digital computing system is disclosed. The circuit comprises a memory array for storing subchannel status words, each of which corresponds to an input/output operation unit. Each subchannel status word includes a timing monitor field having a current count subfield, a count limit subfield, and a command-in-progress bit position. Circuits are provided for incrementing at timed intervals numbers encoded in the current count subfields of those subchannel status words against which a request for an input/output operation is outstanding. A circuit is provided for comparing the numbers encoded in the current count subfields to the count limit subfields to determine if a response to a request for an input/output operation is overdue.

Input/output command timing mechanism

In an image processing system, words of bit length n of video data representing a horizontally scanned image are sequentially loaded in parallel by row into a matrix memory having n rows and in columns. The matrix memory is unloaded sequentially in parallel by column into an array of shift registers of n .times. n bit capacity. Each shift cycle yields a word comprising all bits from the corresponding bit position in each register.

Growing community of inventors

Rochester, MN, United States of America

Thomas S Robinson