Gpt Limited

The Plessey Company Plc

Ericsson Ab

Gec Plessey Telecommunications Limited

Plessey Overseas Limited

Marconi Communications Gmbh

Thomas S Maddern

Richard John Proctor

Alexander S Philip

Geoffrey Chopping

Mark T Jeffrey

John W Ansell

Michael Denis Batts

Bruce Jensen

Peter Bladon

Paul A Smith

James K Saunders

Mark Timothy Jeffrey

Henry Anthony Branfield

Joseph A French

David Ian Scott

An STM telecommunications switch comprising a plurality of parallel data switching planes and a parallel control planes, each plane having an equal number of input ports and output ports and a central switching unit to switch each input port to any output port and wherein the data is switched in octets.

STM switching arrangement

In a partially interconnected topological network having at least six topological nodes, a topological node being a single physical node or a group of interconnected physical nodes or part of a physical node or a group of interconnected physical nodes and parts of physical nodes, each topological node having at least three point-to-point topological links connecting it to some, but not all, of the plurality of topological nodes, there is at least one choice of routing between any two topological nodes, where the choice of routing is either two point-to-point topological links connected in series at another of the topological nodes or a direct point-to-point topological link between the two topological nodes.

Partially interconnected topological network

A network has a plurality of nodes, wherein at least one of the plurality of nodes includes a switch arranged to carry out a Simple Transit Core Function and three or more of the plurality of nodes include a Single Link Interface which Single Link Interface has associated Output Attributes and/or Input Cognizant Attributes. Each Simple Transit Core Function at one node is not logically connected to another Simple Transit Core Function at another node. Each Simple Transit Core Function at one node is logically connected to at least three Single Link Interfaces at other nodes. The nodes including Single Link Interfaces which are connected to one instance of a node arranged to carry out a Simple Transit Core Function are controlled by respective Intercommunicating Connection Acceptance Control Processes according to the respective Output Attributes and/or Input Cognizant Attributes.

Communication network

A communications switch comprising a plurality of numerically identified input traffic ports, a plurality of numerically identified output traffic ports, at least one significant label extractor and at least one numerical processor, the communications switch being arranged whereby each message entering the communication switch by a numerically identified input traffic port contains a header, which header contains a label stack, which label stack includes at least one valid label, of which one valid label is a significant label. The numerical value of the significant label contained within the header of a particular message which entered the communications switch via a particular numerically identified input traffic port is extracted by the at least one significant label extractor and is supplied to one of the at least one numerical processors. The numerical processor uses the significant label of the particular message and the numerical value of the particular numerically identified input traffic port to form a numerical result which directly equates to the number of the numerically identified output traffic port by which the particular message leaves the communications switch and wherein the numerical result is equal to the modulo addition of the numerical value of the significant label and the numerical value of the particular numerically identified input traffic port.

Port label switching

A communications network using Asynchronous Transfer Mode has a head end unit connected to a plurality of groups of network terminations wherein the frequency spectrum of the network is divided into a number of frequency bands, one band of which forms a start-up band used for start-up and configuration of a network termination, the remaining bands each being used for communication between the head end unit and the network terminations within a group subsequent to start-up and configuration. The network may be a Passive Optical Network.

Telecommunications network

In a telecommunications time division multiple (TDMA) optic network system, network termination equipments (NTE's) are enabled to communicate with a head end by the NTE encoding a message as a signal including error correction on the existing signal traffic, monitoring the errors at the head end and extracting the message from the errors.

An ATM telecommunications switch includes a plurality of parallel data switching planes and a parallel central plane, each plane having an equal number of input ports and output ports and a central switching unit to switch each input port to any output port. The switch further includes a first rotator to connect each input port cyclically to each timeslot of the central switching unit and a second rotator to connect each timeslot of the central switching unit cyclically to each output port.

ATM switching arrangement

In a telecommunications duplicated synchronous switch where switching in bit synchronism is carried out and fault detection is by discrepancy checking between the duplicate switch planes, determination of the faulty plane is provided by the data being carried in switched bytes grouped into data frames, each frame carrying check data in respect of data from an earlier frame. Corruption of data in a frame is thus indicated by information in a later frame.

Data verification method

In a telecommunications system in which narrowband or guiding services already exist, different service rates, either fixed or variable may be required. A further service switch is connected in parallel with the existing narrowband or guiding switch, the further service switch being similarly controlled in response to the guiding signalling.

Telecommunications switching

An ATM telecommunications switch includes a plurality of parallel data switching planes and a parallel control plane, each plane having an equal number of input ports and output ports and a central switching unit to switch each input port to any output port. A single data stream is divided between a plurality of input ports and the data is concatenated from a plurality of output ports to reconstitute the data stream. A first rotator connects each input port cyclically to each timelslot of the central switching unit and a second rotator connects each timeslot of the central switching unit cyclically to each output port.

The invention concerns an Asynchronous Transfer Mode Switch having a plurality of input stages (IS1 . . . 1SN) each for receiving a digital data transmission stream (DS1 . . . 256) consisting of a series of cells and wherein each input stage of the switch includes a circuit (52) for determining the destination of the cells of that data stream, and a circuit (63) for disassembling each cell into cell elements and for allocating to each cell element routing data to enable it to be routed across the central stages.

High performance asynchronous transfer mode switch

An asynchronous transfer mode switching arrangement includes a serial to parallel converter arranged to receive input packets of data, which include routing information, in serial form and convert the packets of data to parallel form. A first random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the first random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output. The first random access memory and the output queues are controlled by a memory management arrangement to which is connected a broadcast channel routine second random access memory. The memory management arrangement addresses the broadcast channel routine second random access memory with channel index information, and receives information identifying the required output ports.

Asynchronous transfer mode switching arrangement providing broadcast

A telecommunication apparatus in which data messages are routed across a switch, each message comprising a message portion and an incoming message identity portion, includes circuitry for generating from the incoming message identity portion an outgoing message identity portion, a switching circuit for utilizing the incoming and outgoing message identity portions to route the message to an output port, circuitry for utilizing the outgoing message identity portion to generate a further message identity portion, and comparator circuitry for comparing the incoming and further message identity portions to detect faults.

Message routing check system

An asynchronous time division (ATD) switch for carrying out packet switching. In one embodiment a switch has 256 ports running at 155 M bits and is capable of switching incoming data cells at each of the input ports to any one of 256 output ports. At each input port a switch sequentially distributes the received data cells over 16 outputs each of which is connected to a different DMR circuit. There are 256 DMR circuits each having 16 inputs and 16 outputs. A DMR circuit is a fixed space switching device which has N inputs, N time intervals and N outputs and operates cyclically so that each input goes to each output for 1/Nth of the time. The inner stage of the ATD switch comprises 256 central switches each having 16 inputs and 16 outputs. Each central stage switch has its 16 inputs connected to 16 different DMR circuits. The fourth stage of the switch consists of another array of 256 output DMR circuits with each central switch being connected to 16 different output DMR circuits. Each input DMR has its outputs connected to 16 different output ports. The internal circuitry of the ATD switch runs on 20 M bits. When a data cell is received at an input port its destination is derived from a header attached to the cell. Control circuitry enables the receiving port to request three addresses to query three possible routes through the switch. The ability to provide this series of questions is given by staggering the windows through which an output port can communicate with the central switches. Although data streams are received asynchronously the operation of the ATD switch is synchronous.

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Dorset, United Kingdom

Thomas S Maddern