Bull Hn Information Systems, Inc.

Honeywell Bull, Inc.

Honeywell Information Systems Inc.

Millipore Corporation

Emd Millipore Corporation

Thomas S Hirsch

John L Curley

Richard S Bianchi

Ron B Perry

Thomas O Holtey

William E Woods

James W Keeley

James W Stonier

Keith L Petry

David A Wurz

Richard A Lemay

Philip E Stanley

Gary J Goss

Kin C Yu

Chester M Nibby, Jr

Theodore R Staplin, Jr

Dennis R Flynn

Mary E Tovell

Kenneth J Buck

Marek Grynberg

Ileana S Reisch

John C Penney

A system for centrally managing a set of network-connected laboratory instruments is disclosed. For example, the system includes a centralized database that includes information about the instruments in the system and about the authorized users of the system. In particular, the centralized database indicates which users are authorized to use each of the instruments in the system. The database may also include information about the operations that each user is authorized to perform using the instruments and information indicating whether tests performed by each instrument must be signed using one or more electronic signatures. The system may recognize a number of 'roles,' each of which is associated with a particular set of rights, and may assign one or more roles to each user. Instruments and other elements of the system may access the centralized database over a network to enforce the user rights represented by the information in the database.

Instrument access control system

A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler component is extended to accommodate a number of dual decor commands which invoke host system facilities to execute terminal based commands either synchronously or asynchronously through the automatic creation of host shell mechanisms directly accessible by emulated system users. The server facilities include a network terminal driver (NTD) server for executing emulated system user terminal requests through host system drivers. Additionally, the NTD server includes mechanisms enabling a user to have direct terminal access to host facilities for executing procedures through such shell mechanisms. The mechanisms perform trusted user level validation when each dual decor command is issued and the shell mechanisms use the host access control mechanisms for checking access when the procedure is executed preventing both unauthorized user access and compromises in user data through the improper use of dual decor commands.

Mechanism for enabling emulation system users to directly invoke a

A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service components are extended to accommodate a number of dual decor commands and functions which make host system facilities directly available to ES application programs by concurrent execution of program operations within both the emulator and host system environments. The EMCU includes mechanisms for performing an initial level security validation operation which allows subsequent trusted verification of user identity when dual decor commands or functions are invoked. The server facilities include mechanisms for performing a two-step security validation process for ensuring security relative to preventing both unauthorized user access and compromises in user data through improper use of dual decor commands or functions.

Dual decor capability for a host system which runs emulated application

A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler and file management components are extended to accommodate and to to allow creation and access to linked files within both host and emulated system files. The server facilities include mechanisms for performing trusted user level validation when a command invokes the access of such a linked file and access checking at file access time which ensures security relative to preventing both unauthorized user access and compromises in host file system data by improper use of linked files.

Mechanism for linking together the files of emulated and host system for

A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler and file management components are extended to accommodate dual decor copy command which invokes the file management component to copy files in either direction between the host system and emulated system. The server facilities include mechanisms for performing a trusted user level validation when the dual decor copy command is invoked and access control checking at file access which ensures security relative to preventing both unauthorized user access and compromises in user data through improper use of the copy command.

Copy file mechanism for transferring files between a host system and an

A processing unit couples to a system bus and includes a microprocessor which tightly couples to a local memory. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which couples to the microprocessor and to the system bus. The EEPROM unit stores in first and second separate regions, on-board diagnostic (OBD) routines and boot routines, respectively. The OBD routines are organized into a plurality of categories or phases. The processing unit includes a register accessible only by the microprocessor which, under the control of the OBD routines, is loaded with a number of predetermined values at the beginning of each individual OBD routine for identifying a particular phase and subphase of testing to be performed. Means coupled to the register is directly connected to display a first phase portion of the contents of the register for indicating during which phase of testing a failure occurred. The phase and subphase contents of the register are used to identify the actual test which failed. This information provides an index into a test dictionary which indicates the specific component or group of components which failed.

On-board diagnostic testing

A memory translation mechanism and method executing in a second system to perform first system memory operations for first system executive and user tasks executing on the second system which includes a second system memory organized as a plurality of memory segments, wherein first memory segments are designated to correspond to system memory areas and second memory segments are designated to correspond to user memory areas, and wherein each memory segment corresponds to a combination of a type of first system task and a type of a first system memory area. An interpreter maps by reading an identification of the type of the task corresponding to the first system virtual address from the task type memory and the area type value from the first system virtual address and determining a memory segment corresponding to the type of the first system task and the type of first system area referenced by the first system virtual address. The interpreter maps the identified segment to a memory pool identifier wherein each memory pool identifier corresponds to a task. The second system includes a plurality of pseudo device drivers corresponding to first system input/output devices. Each pseudo device driver includes a segment mapping mechanism which includes a segment pool for storing entries relating memory pool identifiers and providing a corresponding base address identifying the location of the corresponding memory segment in the second system memory.

Emulating the memory functions of a first system on a second system

A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.

Power-on sequencing apparatus for initializing and testing a system

A protection mechanism includes means for taking an input binary value and generating a unique key value as well as performing the reverse operation of taking a key value and generating an input binary value. The mechanism includes a scrambler which includes an array having a number of multibit container locations for storing a unique sequence of random numbers. The scrambler forms another binary value by rearranging the bits of the input binary value as a function of the random number values in addition to altering the states of such bits as a function of the random number values and the numeric bit position values of sources of the input binary bits. The resulting binary value is applied to an alphanumeric encoder which converts the binary value into a series of alphanumeric characters containing a valid key value.

Software data protection mechanism

A data processing system is disclosed in which a plurality of central processing units have access to all the system resources, i.e., have a peer relationship. During initialization of the data processing system, all the system resources are allocated to the individual central processing units according to a preselected distribution procedure, the identification of available resources thereafter being stored in the files of the individual central processing units. During the operation of the data processing system, the resources can be reallocated by a predetermined procedure. The central processing units entering such a relationship are required to include apparatus and/or software procedures that prevent access to system resources not assigned thereto. A mail box procedure, using locations in the main memory unit permit communication between the central processing units and are used in the dynamic allocation of resources.

Apparatus and method for a data processing system having a peer

In a data processing system having a plurality of non-homogeneous central processing units, apparatus is disclosed that permits a central processing unit not having mechanisms for protection of the allocation of resources to be coupled to the data processing system while preserving a peer relationship among the central processing units. The protection apparatus is interposed between the coupled central processing unit and the system bus and reviews each access to data processing system resources to insure that the accessed system resource is available to the associated data processing system. In addition, the apparatus permits initialization procedures without interprocessor conflict, provides status information from the coupled central processing unit to a requesting central processing unit and permits selected control signals to be applied to the coupled central processing unit.

Apparatus and method for alterable resource partitioning enforcement in

A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.

Facility for passing data used by one operating system to a replacement

A computer system is described wherein two independent processors communicate via a bus system and operate substantially concurrently, each computer having its own operating system software and share a common memory. The architecture of the computer system is such that one of the processors is allocated the bulk of memory band-width with the other processor taking the remainder. Arbitration for memory allocation is accomplished via a combination of a new firmware instruction and a semaphore.

Microcomputer system with independent operating systems

One or more queue structures in a data processing system may include a threaded list of frames which are enqueued or dequeued from the list in accordance with four instructions wherein each list is tied to a so-called lock or control frame with synchronization for multiple processing units. Multiple lock frames and accordingly multiple lists of frames may be coupled in the system for the purpose of accomplishing the various tasks necessary.

Growing community of inventors

Bedford, MA, United States of America

Thomas S Hirsch