International Business Machines Corporation

Other

Thomas S Barnett

Matthew Sean Grady

Tange Nan Barbour

Michael Richard Ouellette

William Vincent Huott

Jeanne P Bickford

Nazmul Habib

Susan K Lichtensteiger

Alan Weger

Kerry A Kravec

Wing L Lai

Raymond J Rosner

Sebnem Jaji

Brian M Trapp

Jeanne Paulette Spence Bickford

Kathleen G Purdy

Rashmi D Chatty

Gie Lee

William Y Chang

An apparatus, method, and program product are provided to predict yield loss associated with performance screens or leakage screens. A leakage model is correlated to an on-chip measurement. Current limited yields are determined from the leakage model. A database is formed relating performance sigma cut-points to the circuit limited yields. A product is quoted based on the circuit limited yield for one of the performance sigma cut-points taken from the database. The quote is tied to the product design and testing.

Methods, apparatus, and program products to optimize semiconductor product yield prediction for performance and leakage screens

A method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.

Equivalent gate count yield estimation for integrated circuit devices

The carpenter saw transporter assembly () includes a rectangular plate () with a flange () for supporting the saw machine (). A plurality of wheel assemblies () are mounted on the flange () for transporting the saw machine (). A mounting rail () has a width (W) less than the width (W) of the plate () and is disposed on the plate () and presents male or female undercuts () between a top portion () and a bottom portion (). The saw machine () includes clamps () that can be inserted under and mechanically retained by the undercuts (). A handle tunnel () extends into the mounting rail () for disposing a slidable handle (). A locking mechanism () is disposed on the mounting rail () for locking the handle () in various positions. A plurality of docking strips () are disposed on the plate () for elevating the position of which the clamps () are received and eliminating mechanical contacts between the plate () and the cranks ().

Carpenter saw transporter assembly

A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.

Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability

A statistical method is described for reliability selection of dies on semiconductor wafers using critical wafer yield parameters. This is combined with other data from the wafer or module level reliability screens (such as voltage screen or burn-in) to obtain the relative latent defect density. Finally the modeled results are compared with actual results to demonstrate confidence in the model.

Method of statistical binning for reliability selection

Growing community of inventors

Jericho, VT, United States of America

Thomas S Barnett