Allegro Microsystems, LLC

Thomas Ross

James McIntosh

Gianluca Allegrini

Michael James Munroe

Aldo Togneri

Robert Douglas Christie

Yi Li

James Mcintosh

A CAN transmitter includes an output branch, a replica branch including a replica of the output branch, and a feedback network. The output branch includes a first resistive element controlled by a first bias voltage and a second resistive element controlled by a second bias voltage. The replica branch has a feedback node that is replicated at a midpoint between the CANH bus terminal and the CANL bus terminal. The feedback network has a first input coupled to the feedback node, a second input configured to receive a midpoint reference voltage indicative of a desired midpoint voltage between the CANH and CANL terminals, and an output at which the first bias voltage is provided. A resistance controller is coupled to a control terminal of the second resistive element and configured to generate the second bias voltage based on a predetermined reference voltage and a bias current.

Controller area network (CAN) transmitter

An integrated circuit (IC) includes a level shifter coupled to receive a first supply voltage and a second supply voltage and configured to generate a first output signal and a second output signal in response to an input command signal and an edge detector configured to detect an edge on the second supply voltage and to sink a current from the level shifter in response to detection of the edge in order to prevent a change in logic state of the first output signal or the second output signal. The edge detector can include a positive edge detector configured to generate a positive edge signal in response to detection of a positive going edge of greater than a first predetermined slew rate and a negative edge detector configured to generate a negative edge signal in response to detection of a negative going edge of greater than a second predetermined slew rate.

Level shifter with immunity to state changes in response to high slew rate signals

In one aspect, a circuit includes a gate driver having a first input connected to a first node and a second input connected to a second node; an epi diode connected to the first node; a switch connected to the first node; a capacitor having a top plate connected to the switch and a bottom plate connected to the second node; and a first clamp connected the first node and to the second node. The switch being open isolates the first node from negative transient effects from the top plate of the capacitor.

Gate driver isolating circuit

In one aspect, a gate driver circuit includes a gate driver having a first input connected to a first node and a second input connected to a second node. The gate driver circuit also includes a current source circuit that includes a first transistor and a capacitor having a top plate connected to the source of the first transistor and a bottom plate connected to ground. The gate driver circuit further includes a switch that includes a second transistor. A gate of the second transistor is connected to a drain of the first transistor and a source of the second transistor is connected to the first node.

Switch turn on in a gate driver circuit

In one aspect, a gate driver circuit includes a clamp circuit connecting a first node to a second node. The clamp circuit is configured to provide a clamp voltage. The gate driver circuit also includes a first driver connected to the first node and to the second node. The first driver comprising a first input configured to receive the clamp voltage from the clamp circuit. The gate driver circuit further includes a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver. The first transistor has a gate-to-source voltage and an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor.

Gate driver circuit providing an output voltage that is clamped

In one aspect, an integrated circuit (IC) includes a level shifter configured to generate a first output signal and a second output signal, and to receive an input voltage, a first supply voltage and a second supply voltage; and a state reinforcement circuit configured to maintain a logical state of the second output signal in response to the first supply voltage having a voltage below ground and the input voltage is logical high. If the input voltage is logical high, then the first output signal is logical low and the second output signal is logical high; and, if the input voltage is logical low, the first output signal is logical high and the second output signal is logical low.

Level shifter with state reinforcement circuit

A charge pump includes a first power source having a voltage Vgenerated from a regulated and circuit-limiter supply, a second power source having a voltage Vand a top-off capacitor adapted to be charged to a voltage of the high of Vor Vto a limit of a voltage clamp across the top-off capacitor.

Top-off charge pump and methods of operating same

A multi-mode charge pump generates a regulated voltage at an output node from a battery input voltage. The multi-mode charge pump has a plurality of flying capacitors and a plurality of switches coupled to the flying capacitors in order to selectively couple the flying capacitors to the battery, the output node or a reference potential. The regulated voltage is provided across a storage capacitor coupled to the flying capacitors, and the regulated voltage is input to a comparator. The comparator also receives a reference voltage and compares the regulated voltage to the reference voltage to generates an asynchronous regulation signal. A controller in the multi-mode charge pump can automatically transition between operation modes such as a buck mode, a doubler mode and a tripler mode by controlling actuation of the switches in response to the asynchronous regulation signal and clock signals.

Multi-mode charge pump

Described embodiments provide a transmitter for transmitting data over a serial bus coupled to the transmitter. The transmitter includes a controller to generate data for transmission by the transmitter. A transmit driver is coupled to the controller. The transmit driver, in response to the generated data for transmission, generates logic transitions on the serial bus. The transmit driver generates low-to-high logic transitions on the serial bus by charging the serial bus by a bus current based on (i) a predetermined initial bias level for a first time period, and (ii) a first predetermined maximum bias level for a second time period. The transmit driver generates high-to-low logic transitions on the serial bus by discharging the serial bus by a bus current based on (i) a pre-charged level of the transmit driver, and (ii) a second predetermined maximum bias level for a third time period.

Non-linear transmit biasing for a serial bus transmitter

Described embodiments provide circuits, systems and methods for controlling operation of brushless direct current motors that include a plurality of windings. A gate driver provides control signals to switching elements that control a voltage applied to each of the windings of the motor. A zero crossing detector detects zero crossings of a voltage applied to the windings and transitions a zero crossing signal between a first logic level and a second logic level based on the detected zero crossings. A position estimator estimates an angular position of the motor, and counts in a first direction based on the first logic level of the zero crossing signal, and in a second direction based on the second logic level of the zero crossing signal. An observer determines a value of the counter after an elapsed time, and generates an angular position signal based upon the value of the counter.

Sensorless brushless direct current (BLDC) motor position control

A driver circuit is provided for driving a load, such as a multi-phase motor. The driver circuit includes a gate driver for providing a control signal to switching elements coupled to the driver circuit. A first switching element is coupled between a high supply voltage and a switching node of the load, and a second switching element is coupled between the switching node and a low supply voltage. To detect zero crossings of a current through the load, a zero crossing detector includes a first counter coupled to the switching node and a second counter coupled to the control signal. The first counter and second counter count in a predetermined direction based on a detected voltage of the switching node and based on a detected voltage of the control signal, respectively. The zero crossing detector generates an output signal based upon the difference between the first and the second counter.

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Livingston, United Kingdom

Thomas Ross