Synopsys, Inc.

Thomas Robert Shiple

James Herbert Kukula

Pei-Hsin Ho

Prashant Saxena

Rajeev Kumar Ranjan

Stephen M Plaza

A multi-mode redundancy removal method is provided. In this method, after accessing the design, a full-scale redundancy removal using fault simulation can be started. When a predetermined period for performing the full-scale redundancy removal has reached a first cut-off, then the method can determine a location for temporary outputs of the design, create the temporary outputs, and perform a localized redundancy removal up to the temporary outputs. An optimized design based on the full-scale redundancy removal and the localized redundancy removal can be output.

Multi-mode redundancy removal

In a finite state machine (FSM) a set of goal states, to be searched for their reachability from a start state, is defined. An overapproximated path is found from a start state to a goal state by a forward approximation technique. The overapproximated path representation relies upon a partitioning of the state and input bits of FSM. A state matrix of the overapproximated path is organized by time-steps of FSMalong a first dimension and by partitions of FSMstate bits along a second dimension. An underapproximated path, along the path of the stepping stone matrix, is determined. Underapproximation is typically accomplished by simulation. A sequence of states to be output is updated with the underapproximated path. If a start to goal state sequence has been found, the procedure ends. Otherwise, the above steps of over and under approximation are repeated, using the results of the last underapproximation as a start state.

Method and apparatus for formally constraining random simulation

A method and system for an automata-based approach to state reachability of an interacting extended finite state machine. The present invention comprises a computer system having a processor, and a memory coupled to the processor via a bus, the memory containing computer readable instructions which when executed by the processor cause the processor to implement a process in accordance with the present invention. A digital system is modeled as an extended finite state machine. Automata operations are applied to the extended finite state machine to efficiently compute a set of reachable states from an initial state. The design of the system is verified by determining whether the set of reachable states includes an undesirable state.

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Cupertino, CA, United States of America

Thomas Robert Shiple