Raytheon Company

Thomas R Woodall

Douglas Edward Lapp

Milton K Lum

Mark C Hama

Method and systems using stateful encryption for non-bypassable FPGA configuration including receiving, at an FPGA, FPGA-configuration data comprising a cryptographic state to initialize a cryptographic state of the FPGA, and decrypting, at the FPGA, the FPGA-configuration data, wherein decrypting the FPGA-configuration data yields at least a second cryptographic state and decrypted FPGA-configuration data. Embodiments can include receiving, at the FPGA, a challenge message, processing, at the FPGA, the challenge message to yield at least a third cryptographic state and a response, and transmitting the response from the FPGA.

Secure field-programmable gate array (FPGA) architecture

A method and system for configuring a field-programmable gate array (FPGA) includes receiving an encrypted FPGA load-decryption key at an FPGA from a remote key-storage device. The remote key-storage device may be external to and operatively connected with the FPGA. The encrypted FPGA load-decryption key is decrypted using a session key, which may be stored at both the FPGA and the remote key-storage device. Encrypted FPGA-configuration data is received at the FPGA, and decrypted and authenticated using the decrypted FPGA load-decryption key. The decryption of the FPGA-configuration data may indicate a cryptographic state associated with the FPGA-configuration data, which may be used in recurring authentication of the FPGA-configuration data. For recurring authentication, a challenge message may be received at the FPGA from an authentication device, which may be encrypted using the cryptographic state and the session key to generate a response message. The response message may then be sent to the authentication device to determine authenticity of the FPGA-configuration data.

A multi-level security software architecture includes various components configured to provide full data separation across multiple processors while limiting the number and size of high assurance components. The architecture includes a domain separator for ensuring that messages exchanged between domains that are distributed on different microprocessors are securely routed between domain members. The domain separator verifies a message label including a domain identifier provided by a domain gateway and cryptographically binds the message label to each message via cryptographic keys. This prevents misrouting messages caused by accidental or malicious corruption of message labels. Additionally, the domain separator can encrypt messages as necessary to enforce data separation on shared network buses. The domain separator is also responsible for managing the cryptographic keys used to label or encrypt messages.

Multi-level security software architecture

A multi-level secure multi-processor computer architecture. The inventive architecture provides an inexpensive security solution for integrated avionics and includes a plurality of nodes. The nodes are connected via a switch in a network configuration over which data is routed using labels. The switch is controlled to facilitate secure communication of data between the nodes. In the illustrative embodiment, the network is a Fibre Channel network including plural switches in which a system manager node serves to control routing between nodes based on a security policy. Each node has a central processing unit. The system manager is implemented as a node and sets up routing tables for selective connection of the nodes via the switch. The label assignments are stored in Fibre Channel network interface cards disposed on each node. The system manager also sets up label routing tables that authorize the interconnection of selective nodes. The label routing tables are stored in the switch, which in the illustrative implementation is a crossbar switch having a plurality of switch protocol controllers and switch control units. The label assignments and label routing tables are stored in a label authorization table stored in the system manager. After a secure startup, the system allows for communication in accordance with a security policy between nodes to which trusted and/or untrusted hardware is connected and running under trusted and/or untrusted software applications. The software applications may run on commercial off-the-shelf (COTS) operating systems.

Multi-level secure multi-processor computer architecture

A method for detecting entry into a secure area uses a passive entry detector. The secure area has an access door, having a closed position. The passive entry detector comprises a source of energy internal or external to the passive entry detector, an activator for detecting a change in the access door from its closed position, and for releasing the energy in response to the change of the access door from the closed position. The energy is transferred to one or more pseudo random units. Each of the pseudo random units has a plurality of mechanical states. The pseudo random units are responsive to the activator. The activator induces a change of the mechanical states in the pseudo random units upon transfer of energy. The pseudo random units report the mechanical states upon interrogation. Using above passive entry detector, a first interrogation using the interface is performed to create a first record to identify one or more mechanical states with the access door in the closed position. Re-interrogating is performed again after an interval, typically prior to opening the access door from its closed position. This re-interrogating identifies again the mechanical states in the pseudo random units of the passive entry detector and generates a second record. Comparing the first record with the second record determines if the internal mechanical states have been altered during the time interval.

Pseudo&#x2014;random state mechanical switch

A method and apparatus for fault management in a network. A network architecture is disclosed including at least one network switch, several network interface cards, several processors (host) and a network manager. Fault reporting and detection logic is implemented in each switch and in each network interface card. In addition, multiple fault reporting pathways are provided for each switch and each network interface card. As a result, utilizing message exchanges such as Fibre Channel exchange messages, the switch, the network interface cards and the processors (host) are able to autonomously generate and report faults to the network manager. The combined fault reporting enables the network manager to more accurately isolate faults. In addition, because of the autonomous nature of the fault reporting, faults may be detected and corrected prior to the initiation of a communication session.

System and method for real-time fault reporting in switched networks

A stream computer comprises a plurality of interconnected functional units. The functional units are responsive to a data- stream containing data and tokens. The data is to be operated on by one or more of the plurality of interconnected functional units. Digital logic cooperatively associated with one of the functional units adds one or more tokens to the data stream presented to one of the functional units. The tokens are representative of the type of data being generated or received by the functional units. The digital logic also reports the occurrence of said one or more tokens within said data stream without interrupting the data stream. The digital logic reports one or more tokens arriving at one of the functional units as part of the data stream to a graphical programming environment. The graphical programming environment is compatible with human perception. The programming environment compares tokens arriving from the digital logic with stored values within the graphical environment for the tokens so as to identify any errors. An error message is generated by the graphical programming environment whenever the comparison between the tokens and the stored values within the programming environment indicates that the tokens and the stored values do not match. These tokens are reported by the digital logic to a graphical programming environment compatible with human perception.

Growing community of inventors

Valencia, CA, United States of America

Thomas R Woodall