Lsi Logic Corporation

Other

Esilicon Corporation

Adaptive Design Solutions, Inc.

Thomas R Wik

V Swamy Irrinki

Ashok K Kapoor

Raymond T Leung

Alex Owens

Ghasi R Agrawal

Michael Anthony Zampaglione

Tuan L Phan

Myron J Buer

Robin H Passow

Shahryar Aryani

Thien Trieu

Ken Redding

A solar panel that attains very low cost/Watt objectives is achieved by applying an optical concentrator with planar symmetry in combination with a simple 1-axis tracking system. The concentrator uses a Cassegrain optical system to provide moderate concentration factors that can be adjusted by varying the ratio of the focal lengths of the concave and convex reflecting surfaces. Concentrator dimensions can be scaled to any convenient size. They can be arrayed in parallel to form a solar panel that has the same form factor as a 1-sun solar panel. One-axis tracking is achieved by simply rotating the collector elements in synchronism so the sun is maintained in the plane of symmetry for each of the collector elements that comprise the panel.

Low-cost efficient solar panels

A ternary content addressable memory (TCAM) is disclosed. The TCAM includes a memory array, a data match module, and compare circuitry. The memory array stores a data entry for a data word and a corresponding duplicate data entry for the data word. The data match module compares the data entry to an input word to produce a first match output, and compares the duplicate data entry to the input word to produce a second match output. The compare circuitry compares the first match output and the second match output.

Error detection and correction in ternary content addressable memory (TCAM)

A binary content addressable memory (BCAM) is disclosed. The BCAM includes a memory array, data signature circuitry, and a data match module and compare circuitry. The memory array is configured to store a data entry for a data word and a corresponding data signature for the data entry. The data signature circuitry is configured to calculate the data signature for the data entry and to calculate the data signature for an input word. The data match module compares the data entry to the input word to produce a content match output, and compares the data signature for the data entry to the data signature of the input word to produce a signature match output. The compare circuitry compares the content match output and the data signature match output.

Error detection and correction in binary content addressable memory (BCAM)

A low-cost solar collector employs a concave reflecting surface and a convex reflecting surface configured as a cylindrical Cassegrain optical system with planar symmetry to concentrate sunlight for photovoltaic solar panels. The collector achieves high concentration factors exceeding 20&#xd7; and maintains focus of concentrated sunlight on the photovoltaic cells using a simple mechanical means to rotate the collector. A plurality of solar collectors is arranged in parallel in a conventional solar panel form factor and driven by a single drive system to maintain the sun continuously in the plane of symmetry of each of the solar collectors that comprise the solar panel. This reduces the area of photovoltaic cells required to convert a given quantity of light energy to electrical energy. Cost of electrical energy generated is reduced significantly because the cost per unit area of the solar collectors is much less than the cost of photovoltaic cells.

Low-cost solar collector

Power savings are achieved for digital data transport over short distances by using the characteristics of resonant LC circuits. Economy of circuit elements is achieved by enabling a single pair of resonant circuits to drive large numbers of digital data lines or nodes in parallel. This maximizes power efficiency and minimizes area and cost. Resistance is minimized by insuring that all switches in the current path are fully 'ON' whenever significant current is flowing through them. All other parasitic resistances in the circuits, consisting primarily of parasitic interconnect resistances, are minimized. This enables the data transmission circuits to achieve maximum Q or quality factor, which minimizes power dissipation.

Resonant digital data transmission

A crossbar switch is optimized for area, performance, and power by grouping the data lines that comprise the input ports and output ports of the switch into a plurality of separate cross-point blocks. Each cross-point block contains a complete set of input and output ports but the number of data lines comprising the input and output ports of each separate cross-point block is reduced to fraction of the number of data lines contained in each port of the crossbar switch. This fraction is equal to one divided by the number of separate cross-point blocks. Area, performance, and power of the crossbar switch are improved provided the area of the crossbar switch without grouping of data lines into separate cross-point blocks is determined by the pitch of the data lines rather than the area of the cross-point circuits. The number of blocks can be selected to optimize area, performance and power.

Crossbar switch with grouped inputs and outputs

Conditioning logic modifies the electrical characteristics of conventional logic circuits to improve speed, power, and timing margins. This is accomplished by adding circuitry to pre-condition the state of the circuit to optimize any desired transition. Basic functionality of the logic circuit in response to the inputs is unchanged, but output delays, power dissipation, and timing margins can be improved and other characteristics of the circuit can also be controlled by the conditioning circuitry such as voltage levels, leakage current and power dissipation. The effect of the conditioning circuitry on the electrical and timing parameters of the logic function is controlled by binary feedback inputs to the conditioning circuitry. Feedback inputs can be generated from any combination of logic states and clock inputs including clock inputs and logic inputs not used in the logic function receiving the feedback input.

Conditioning logic technology

A memory array has memory elements arranged in rows and columns. Each column has a respective bit line. A plurality of bit line input-output nodes are each switchably coupled to either a respective one of the bit lines or another one of the bit lines.

Integrated circuit memory having column redundancy

The present invention is directed to a system and method of compensating for coupling capacitance between bit lines in multi-port memories. The complementary bit lines are switched between a core cell and a modified core cell. The modified core cell may invert the connections to the access transistors. This results in the writing of data into the cell correctly while compensating for coupling capacitance.

Way to compensate the effect of coupling between bitlines in a multi-port memories

A multi-port semiconductor memory includes first and second data ports and a plurality of memory cells arranged in rows and columns. Each column comprises first and second pairs of complementary bit lines, which are coupled to each of the memory cells in that column. The first pair of bit lines cross one another between every N and N&plus;1 of the memory cells the column, where N&equals;2,and M is an integer variable greater than zero. A data inversion circuit is coupled between the first pair of bit lines and the first data port, which selectively inverts the first pair of bit lines as a function of the first port's (M&plus;1)th row address input bit only, as measured from the least significant row address input bit.

Multi-port semiconductor memory and compiler having capacitance compensation

A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit includes an array of cells in which each cell has multiple storage elements. At least one of the storage elements performs its function in a different way than the rest of the storage elements. This use of multiple storage mechanisms allows for a greater freedom in memory cell design and allows for the simultaneous storage of multiple states in a single memory cell. Broadly speaking, the present invention contemplates a memory core comprising an address decoder, an array of cells, and a sense amplifier. The address decoder is configured to receive an address and responsively assert a selected word line. The array of cells includes a selected cell coupled to the selected word line, and each cell in the array of cells includes at least two storage elements. A first storage element is configured with a first state which is one of a first plurality of states, and a second storage element is configured with a second state which is one of a second, different plurality of states. The sense amplifier is coupled to the selected cell via a bit line and configured to detect the first and second states. Each cell may further include a third storage element configured with a third state which is one of a third plurality of states. In this case, the sense amplifier is also configured to detect the third state. Examples of candidate storage states include charges on a capacitance, conductivities of transistors, resistances between terminals, turn-on voltages of transistors, currents flowing in closed loops, and orientations of magnetized material.

Memory system using multiple storage mechanisms to enable storage and

A method is provided for using twisted bit or signal lines and routing restrictions on the logic signal lines to pass logic signals over an on-chip memory. In one embodiment, the memory array includes complementary bitlines which are provided with periodic twists, and the logic signal routing is restricted in that logic signals are either routed perpendicular to the bit lines, or they are routed parallel to the bit lines in such a manner as to ensure equal coupling to both B and B'. The equal coupling is provided by either restricting the length of the logic signal line segment to an integral number of twist wavelengths, or by placing the logic signal line segment so that its midpoint rests on a twist centerline. In another embodiment, the memory array includes bitlines running parallel to a bitline axis, and complementary logic signal lines are routed in pairs. The logic signal routing is restricted in that logic signals are either routed perpendicular to the bitline axis, or they are routed parallel to the bitlines in such a manner as to ensure equal coupling to both B and B'. The equal coupling is provided by either placing a twist at the midpoint of the complementary logic signal line segment, or by placing periodic twists in the complementary logic signal line segment and restricting the length of the segment to an integer number of twist wavelengths.

Method and system which permits logic signal routing over on-chip

A test method for a memory device wherein failures that may only occur under specified worst-case conditions are converted to hard functional failures. These locations are subsequently detected and remapped by built-in self test (BIST) and built-in self-repair (BISR) circuitry. First, a test suite is performed on a memory array which includes redundant row and column locations. Typically, this test suite is performed under conditions which are most likely to induce failure. Row and column locations that are determined to be malfunctioning are scanned out of the memory device, along with the number of available redundant rows and columns. If there are sufficient redundant locations, the failing rows and columns are permanently disabled by blowing each of the corresponding fuse links. When power is subsequently applied to the memory device, BIST will detect rows and columns, including those permanently disabled, with hard functional failures. Accesses to these locations may then be redirected by BISR circuitry. The test suite may then be re-executed, and the device deemed defective if additional errors are found. Rows and columns in the memory array that are prone to failure are thus never enabled. Additionally, the BIST and BISR circuitry provides the ability to verify basic memory functionality and remap failing addresses on each application of power to the device. Test coverage of the memory array is advantageously increased.

Method of testing memory operations employing self-repair circuitry and

A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

Memory cell capable of storing more than two logic states by using

A method for testing refresh operations of a memory array wherein subthreshold leakage current may be set to near worst-case conditions. The memory array includes a first row of memory cells having a first memory cell configured to store a first memory value, and a second row of memory cells having a second memory cell configured to store a second memory value. The method comprises storing a logic high value to the first memory cell as the first memory value, followed by storing a logic low value to the second memory cell as the second memory value. The method further comprises repeatedly driving a write bit line coupled to both the first and second memory cells at a logic low level for a period of a time equal to a refresh interval corresponding to the first memory cell. Additionally, the method includes subsequently reading the first memory value from the first memory cell. Finally, the method includes indicating that the first memory cell is operating correctly if the first memory value is still equal to a logic high value, or indicating that the first memory value is malfunctioning if the first memory value is equal to a logic low value. Driving the write bit line low may be accomplished by repetitively reading the second memory cell. The same effect may alternately be achieved by repetitively writing a logic low value to the second memory cell. By keeping the write bit line at a logic low level during testing of refresh operations, the subthreshold leakage current through the write transistor of the first memory cell may be increased. This accelerates the discharge of the first memory value, and insures testing is performed near worst-case conditions.

Growing community of inventors

Livermore, CA, United States of America

Thomas R Wik