Adaptec, Inc.

Texas Instruments Corporation

Thomas R Schneider

Takashi Asami

A Fiber Channel host bus adapter has a low power, high speed serial to parallel data converter for converting asynchronous serial data into clock aligned, framed, parallel data utilizing a serial in, parallel out register for receiving asynchronous serial data and for providing unframed parallel data. An array of parallel in, parallel out registers is configured to receive parallel data from the serial in, parallel out data register and move the data in a parallel fashion between the parallel in, parallel out registers thereof. A pattern detection circuit identifies a location of a delimiter character within the array of a parallel in, parallel out registers. A selection circuit reads desired data bits from the array of parallel in, parallel out registers in a parallel fashion, based upon the location of the delimiter character, to define a framed parallel output word. A data alignment circuit aligns the framed parallel output word with respect to a clock to define a clock aligned, framed parallel output word.

Fibre channel host bus adapter having multi-frequency clock buffer for reduced power consumption

A pseudo-random built in self test pattern generator is constructed of eight sequential D-flip flops and configured to output 10-bit wide pattern data which conforms to the 8B/1OB transmission protocol. The first and fifth D-flip flops of the array have their outputs split, with one leg of the split directly defining a character bit and the other leg of the split defining an inverted character bit. The outputs of the first, second, seventh and eighth D-flip flops are directed to a four input EXOR gate whose output is connected to the D input of the first D-flip flop of the array. Configured as a recirculating feed back loop, the pattern generator defines a sequence of,-bit patterns in which no more than five sequential 1s or five sequential 0s are generated either within a pattern or on pattern boundaries. The pattern generator provides 255 Fiber Channel-type transmission characters to a Fiber Channel-type transceiver circuit which serializes the characters into a 1.06 GHz serial datastream and then deserializes the datastream into 10-bit transmission characters. The received transmission characters are analyzed and if they match with patterns transmitted, the transceiver circuit is deemed to be correctly operating at a 1.06 GHz characteristic frequency.

Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator

The present invention provides a precharge circuit for precharging bit lines coupled to a read sense amplifier and a RAM cell. The precharge circuit includes a set of precharge transistors, a first transistor, and a transistor pair. The set of precharge transistors is coupled to said bit lines for precharging said bit lines with one precharge transistor per bit line. The first transistor is coupled to turn on said set of precharge transistors when said RAM cell is not being read. The first transistor is operative to reduce the gate-to-source voltage V.sub.GS of said set of precharge transistors such that each of said precharge transistors output a reduced precharge voltage to the associated bit line. The transistor pair is coupled to said set of precharge transistors and is operative to switch said precharge transistors for reading said RAM cell. In this configuration, the RAM cell outputs a differential signal onto said bit lines when said precharge transistors are turned off. The read sense amplifier monitors said bit lines to detect said differential signal on said bit lines as a data bit.

NFET/PFET RAM precharge circuitry to minimize read sense amp operational

An integrated circuit provides for an output driver having a quick turn-on characteristic as well as a maximum V.sub.OH level limited to the maximum SCSI specification limit. The output driver's V.sub.OH is controlled by a resistor divider network, connected between a pull-up signal source and a pull-up output device, and which functions to reduce the gate voltage on the output device such that its maximum V.sub.OH level is limited to the SCSI specification. The quick turn-on characteristic is implemented by coupling a transfer gate in parallel with the series resistor of the resistor divider network, and bypassing the series resistor during a first portion of the pull-up turn-on time of the output driver. A feedback circuit is connected between the output driver output and the transfer gate bypass circuit, in order to turn the transfer gate off when the output voltage reaches a particular trigger value, thus removing the bypass from the series resistor and allowing the resistor divider network to function normally and limit the output driver's pull-up to the maximum SCSI V.sub.OH limit. The transfer gate is further configured to allow an SCSI device incorporating the circuit to be hot-switched onto and off of an active SCSI bus.

Hot-switchable SCSI controller having output drivers with quick turn-on

An integrated circuit provides for adjustable slew rate control for both rising and falling edges of an output provided to an SCSI bus. Slew rate is controlled by adaptively varying the charge and/or discharge rate of the gate electrode of an output driver's N-channel pull-down transistor. Charge time and, thus, the falling edge slew rate, is adaptively varied by selectively adding the current source P-channel transistors to a current bus coupled to the gate electrode of the pull-down transistor. Similarly, the discharge rate and, thus, the rising edge slew rate, is adaptively adjusted by selectively switching current sink transistors on to the current bus coupled to the pull-down transistor's gate electrode. The amount of currents sourced or sunk is determined by varying the W/L ratios of both the current source and current sink transistors.

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Anaheim, CA, United States of America

Thomas R Schneider