International Business Machines Corporation

Endicott Interconnect Technologies, Inc.

Thomas R Miller

Voya Rista Markovich

Anilkumar Chinuprasad Bhatt

Michael Wozniak

John M Lauffer

William John Rudik

Gerald Walter Jones

Konstantinos I Papathomas

Frank Daniel Egitto

Luis Jesus Matienzo

William E Wilson

Roy H Magnuson

Edmond Otto Fey

Allen Frederick Moring

Anastasios Peter Angelopoulos

James Paul Walsh

Douglas Oliver Powell

Brian Eugene Curcio

Raymond Thomas Galasco

Kristen Ann Stauffer

Curtis L Miller

Anita Sargent

Robert J Testa

John Ulrich Knickerbocker

Robert Maynard Japp

Carlos Juan Sambucetti

James Warren Wilson

Ashwinkumar C Bhatt

Stephen L Tisdale

Robert David Sebesta

Subahu Dhirubhai Desai

William D Taylor

Michael James Cummings

Manh-Quan Tam Nguyen

Edward Lee Arrington

Robert Jeffrey Day

Kenneth J Lubert

John Christopher Camp

Kevin P Unger

Curtis Michael Gunther

James Robert Wilcox

Timothy Leroy Wells

James R Stack

Norman A Card

Michael Vito Longo

Joseph J Sniezek

James P Paoletti

David Anton Klueppel

Duane A Stanke

Voya P Markovich

A method of making a printed circuit board in which at least two circuitized substrates are aligned and bonded together (e.g., using lamination). A gasket is provided on one of these and a facing circuitized portion on the other. The gasket forms an effective seal about the circuitized portion to prevent heated dielectric material from contacting the circuitry. After bonding, parts of the bonded structure, including the gasket, are removed to leave a projecting edge portion having circuitry thereon. This edge portion is then adapted for being positioned within an edge connector.

Method of providing a printed circuit board with an edge connection portion

Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

Method of fabricating a BGA package having decreased adhesion

A method of making a circuitized substrate assembly in which two or more subassemblies are aligned and bonded together. The bonding, preferably using lamination, results in effective electrical connections being formed between respective pairs of conductors of the subassemblies in such a manner that the metallurgies of the conductors, and those of an interim metallic solder paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies is forced to flow to engage and surround the conductor coupling, without adversely affecting the electrical connection formed.

Method of making circuitized substrate with solder paste connections

A PWB or multilayer board with circuit traces is treated by a process that serves to reduce the incident of failure of the board. The process includes the steps of applying a thin commoning layer of copper onto a catalyzed surface of the board substrate and the circuit lines. A photoresist is then applied over the commoning layer after which the photoresist is removed only from the commoning material over the circuit lines. A thin layer of a more noble metal, such as nickel, is electrodeposited over the exposed conductive layer. This is followed by a gold layer electrodeposited over the nickel in close registry therewith. The process provides the traces with a conforming nickel/gold layer that extends down the side of the traces. This reduces the tendency of a subsequent copper etch step from undercutting the nickel/gold, thereby causing slivers that could cause short circuiting between adjacent circuit patterns.

Method of making a printed wiring board with conformally plated circuit traces

Method and structure for an organic package with improved BGA life

A layer for use in a modular assemblage for supporting ICES is formed with metal contacts for assembly by making a sandwich of metal interconnect members between two layers of dielectric; drilling holes through the dielectric, stopping on a metal layer bonded to the bottom surface of the module; forming blind holes stopping on the interconnect members; and plating metal through the volume of the via, both full and blind holes, thereby forming vertical and horizontal connections in a layer that be stacked to form complex interconnect assemblies.

Joining member for Z-interconnect in electronic devices without conductive paste

A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

Method and structure for small pitch z-axis electrical interconnections

A method of making a circuitized substrate in which a commoning layer is used to form multiple, substantially vertically aligned conductive openings in a multilayered component such as a laminate interposer for coupling a chip to a printed circuit board or the like. The structure, including such a chip and circuit board is ideally suited for use within an information handling system.

Circuitized substrate and method of making same

A colloidal metal seed formulation useful for catalytically activating a surface of a non-conductive dielectric substrate in an electroless plating process is provided. The colloidal metal seed formulation includes stannous chloride, palladium chloride, HCl and a surfactant selected from a diphenyloxide disulfonic acid or alkali or alkaline earth metal salt thereof, CHO, an alcohol alkoxylate and mixtures thereof. A method of electroless plating of a conductive metal onto a non-conductive dielectric substrate using the colloidal metal seed formulation is also provided.

Colloidal seed formulation for printed circuit board metallization

A method for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, disclosed is the provision of a method for producing an impedance controlled printed circuit wiring board. Also, there is the provision of a method for producing high speed printed wiring boards with multiple differential impedance controlled layers.

Method for producing an electronic package possessing controlled impedance characteristics

Printed wiring board with conformally plated circuit traces

Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Printed wiring board

A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.

Copper plated PTH barrels and methods for fabricating

A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

Fine pitch circuitization with filled plated through holes

Growing community of inventors

Endwell, NY, United States of America

Thomas R Miller