Intel Corporation

Thomas R Huff

Shreekant S Thakkar

Patrice L Roussel

Vladimir M Pentkovski

Hsien-Cheng Emile Hsieh

Mohammad A F Abdallah

Elmoustapha Ould-Ahmed-Vall

Bret L Toll

Jesus Corbal

Jason W Brandt

Edward Thomas Grochowski

Stephen H Gunther

David B Papworth

Robert S Chappell

James D Allen

Buford M Guy

Christopher J Hughes

Mohammad A Abdallah

Srinivas Chennupaty

Lihu Rappoport

Ronak Singhal

Lance E Hacking

Seyed Yahya Sotoudeh

Gregory C Parrish

Per H Hammarlund

Yen-Kuang Chen

Stephen Anthony Fischer

Roger A Golliver

William W Macy, Jr

Herbert H Hum

Bryant E Bigbee

Matthew J Holliman

Prasad Modali

Nathaniel Hoffman

William C Alexander, Iii

Chien-Yu Huang, Legal Representative

Mohammad Af Abdallah

Srinivas Channupaty

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Apparatuses and methods for a processor architecture

Zeroing a cache line

A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. One or more numbers in the floating point format are converted to the integer format and placed in a register of a second set of architectural registers in a packed format. Conversion from integer format to floating point format is performed in a similar manner. A floating point arithmetic apparatus is described that provides for converting a plurality of numbers between integer formats and a floating point formats, further providing for conversion operations that require a greater data path width than floating-point arithmetic operations.

Method and apparatus for floating point operations and format conversion operations

A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.

Method and apparatus for performing cache segment flush and cache segment invalidation operations

The present invention discloses a method and apparatus for saving and restoring registers. A single instruction is decoded. The single instruction moves contents of a plurality of registers associated with a functional unit in a processor to a memory; the processor operates under a plurality of operational modes and operand sizes. The single instruction arranges the contents in the memory according to a predetermined format into a plurality of groups, each group is aligned at an address boundary which corresponds to a multiple of 2bytes. The predetermined format is constant for the plurality of operational modes and operand sizes. The single instruction retains the contents of the plurality of registers after moving.

Efficient saving and restoring state in task switching

A method and apparatus for variable length coding is described. A method comprises receiving a group of data having a group of set values, identifying a group of positions of the group of set values within the group of data without branching, for each of the group of positions, encoding a run of non-set values preceding each of the group of positions.

Method and apparatus for variable length coding

A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

Conversion between packed floating point data and packed 32-bit integer data in different architectural registers

A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 8-bit number in the integer format. The 8-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.

Conversion from packed floating point data to packed 8-bit integer data in different architectural registers

A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.

Data conversion between floating point packed format and integer scalar format

An apparatus and method for performing conversion of graphical data format is disclosed. A matrix multiplication is performed on a first set of data and a second set of data to generate a third set of data in a first format. The first and second sets of data represent the graphical data. The third set of data in the first format is transmitted to a graphics card. The third set of data in the first format is converted to a converted set of data in a second format.

Method and apparatus for converting data format to a graphics card

A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.

Cache pollution avoidance instructions

A method and instruction for converting a number from a floating point format to an integer format are described. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the floating point format is converted to at least one 16-bit number in the integer format. The 16-bit number in the integer format is placed in a register of a second set of architectural registers in the packed format.

Conversion from packed floating point data to packed 16-bit integer data in different architectural registers

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Portland, OR, United States of America

Thomas R Huff