Micron Technology Incorporated

Other

Sapidyne Instruments Inc.

Roche Diagnostics Gmbh

Sapidyne, Inc.

Thomas R Glass

Zhiping Yin

Gurtej S Sandhu

Ravi T Iyer

Steven M McDonald

Kunal R Parekh

Mark Fischer

Philip J Ireland

Ardavan Niroomand

Richard D Holscher

Linda K Somerville

Steve J Lackie

Weldon R Hudson

Myron J Block

Kevin H Schofield

The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.

Circuitry and gate stacks

A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers between a reflective surface and another material. The indices of refraction, absorptions, and thicknesses of the at least two anti-reflective coating layers are chosen such that the amplitudes and phase differences of radiation reflected from the anti-reflective coating layers, as well as any other reflective surfaces below the anti-reflective coating layers, mutually cancel when combined. The invention may be practiced using more than two layers of anti-reflective coating. Multiple layers of anti-reflective coating may be used below an inter-level dielectric, in which case they may serve the additional purpose of functioning as an etch-stop.

Photolithography process using multiple anti-reflective coatings

The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.

Use of DAR coating to modulate the efficiency of laser fuse blows

Photolithographic structures using multiple anti-reflecting coatings

The present invention comprises construction of a display from display elements that are actuated using the physical principle of electrowetting. In one embodiment, pores within porous silicon are filled with an ionic and an optically reflective electronic conductor, and actuated by application of an electric potential across the pore. An image is then formed on an array of such pores by applying an appropriate voltage to each pore of the array to create an optical image in the light reflected off the electronic conductors. Such a display may be constructed to have very high resolution, making it desirable for creating real-time holographic images, or for creating high-resolution mask images for use in photolithography.

Electrowetting display

The present invention provides an improved system for detecting the presence or level of an analyte in a sample. In 'competition-like' assays of the present invention, a sample including an analyte is mixed with a second ligand to which the analyte binds, and the mixture is exposed to a solid phase containing a first ligand that can compete with the analyte for binding to the second ligand. According to the present invention, the time of exposure of the mixture to the solid phase is limited so that substantially no dissociation of analyte/second ligand complex occurs. The competition-like assays of the present invention are preferably performed with a solid phase containing a substantial excess of first ligand. In 'sandwich-type' assays of the present invention, a sample including an analyte is contacted with a solid phase including a first ligand that binds the analyte and, simultaneously or subsequently, is contacted with a second ligand that binds the analyte (or the analyte/first ligand complex). The time of contact between the second ligand and the solid phase is limited so that substantially no non-specific binding between the second ligand and the solid phase occurs.

Solid phase assay for detection of ligands

The present invention provides an improved system for detecting the presence or level of an analyte in a sample. In &ldquo;competition-like&rdquo; assays of the present invention, a sample including an analyte is mixed with a second ligand to which the analyte binds, and the mixture is exposed to a solid phase containing a first ligand that can compete with the analyte for binding to the second ligand. According to the present invention, the time of exposure of the mixture to the solid phase is limited so that substantially no dissociation of analyte/second ligand complex occurs. The competition-like assays of the present invention are preferably performed with a solid phase containing a substantial excess of first ligand. In &ldquo;sandwich-type&rdquo; assays of the present invention, a sample including an analyte is contacted with a solid phase including a first ligand that binds the analyte and, simultaneously or subsequently, is contacted with a second ligand that binds the analyte (or the analyte/first ligand complex). The time of contact between the second ligand and the solid phase is limited so that substantially no non-specific binding between the second ligand and the solid phase occurs.

A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.

Isolation using an antireflective coating

A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.

In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer. In another aspect, the invention includes a gate stack forming method, comprising a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide layer; d) forming a silicon nitride layer over the antireflective material layer; e) forming a layer of photoresist over the silicon nitride layer; f) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and g) transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer to pattern the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer into a gate stack. In yet other aspects, the invention encompasses circuitry and gate stacks.

Semiconductor processing methods, semiconductor circuitry, and gate stacks

A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers between a reflective surface and another material. The indices of refraction, absorptions, and thicknesses of the at least two anti-reflective coating layers are chosen such that the amplitudes and phase differences of radiation reflected from the anti-reflective coating, layers, as well as any other reflective surfaces below the anti-reflective coating layers, mutually cancel when combined. The invention may be practiced using more than two layers of anti-reflective coating. Multiple layers of anti-reflective coating may be used below an inter-level dielectric, in which case they may serve the additional purpose of functioning as an etch-stop.

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Idaho City, ID, United States of America

Thomas R Glass