International Business Machines Corporation

Thomas R Bednar

Paul Steven Zuchowski

Scott Whitney Gould

Douglas Willard Stout

David E Lackey

Jeannie H Panner

Paul E Dunn

Douglas Wayne Kemerer

Patrick H Buffet

Timothy W Budell

Thomas Gregory Sopchak

Steven Michael Eustis

Jeffery Howard Oppold

Alain Caron

Leah Marie Pfeifer Pastel

James V Crain, Jr

Donald S Kent

Esmaeil Rahmati

An integrated circuit chip having a contact layer that includes a plurality of Vdd, Vddx, ground and I/O contacts arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. A multilayer X-Y power grid is located beneath the contact layer. A wiring layer is interposed between the contact layer and power grid to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.

Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid

An integrated circuit. The integrated circuit includes a parent terrain; and a hierarchical order of nested voltage islands within the parent terrain, each higher-order voltage island nested within a lower-order voltage island, each nested voltage island having the same hierarchical structure.

Nested voltage island architecture

Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

Macro design techniques to accommodate chip level wiring and circuit placement across the macro

A method and system for locating connector defects in a defective scan chain that has a parallel non-defective scan chain on a different wiring level, with both scan chains being laid out in a regular array pattern. A predetermined bit sequence is scanned into the defective scan chain. The contents of the defective scan chain are then parallel shifted into the non-defective scan chain. The contents of the non-defective scan chain is then scanned out and compared with the predetermined bit sequence. The comparison of the scanned out bits with the predetermined bit sequence facilitates locating both physically and logically where a connector defect has occurred in the defective scan chain.

Diagnosable scan chain

A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.

Voltage island chip implementation

A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.

Voltage island design planning

A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.

Global voltage buffer for voltage islands

A structure and method for improving yield during physical chip design comprises identifying non-critically timed minimum groundrule cells located within the chip design, determining if whitespace exists around the non-critically timed minimum groundrule cells, and replacing the non-critically timed minimum groundrule cells that have the whitespace with non-minimum groundrule cells if the replacing leaves a functionality of the circuit unaltered.

Growing community of inventors

Essex Junction, VT, United States of America

Thomas R Bednar