Standard Microsystems Corporation

Burr-brown Corporation

Other

Microchip Technology Inc.

Thomas R Anderson

Scott Cameron McLeod

Joel Martin Halbert

Myron J Koen

Steven Burstein

Leonid A Bekker

William Castellano

Howard L Skolnik

Bruce C Trump

Razvan Ionut Ungureanu

A power meter includes a sampling circuit configured to initially make electrical measurements of a unit under test at a first sampling frequency. The power meter includes an adaptive circuit. The power meter includes an accumulator configured to accumulate electrical measurements of the unit under test from the sampling circuit. After a change in sampling frequency from the first sampling frequency to a second sampling frequency, the sampling circuit makes second electrical measurements at the second sampling frequency. The adaptive circuit is configured to adjust the second electrical measurements from the sampling circuit according to a factor. The factor is based on a relationship between the first sampling frequency and the second sampling frequency. The adjustment yields adjusted second electrical measurements. The accumulator is further configured to accumulate the adjusted second electrical measurements.

Adaptive power measurement accumulator with a changing sampling frequency

In one set of embodiments, trimming of a reference, which may be a bandgap reference and which is configured on an integrated circuit, may be controlled by an algorithm executed by logic circuitry also configured on the integrated circuit. The bandgap reference may be configured to generate a reference voltage provided to an analog to digital converter (ADC) comprised in a temperature sensor that may also be configured on the integrated circuit. The logic circuitry may be configured to execute one or more of a variety of test algorithms, for example a Successive Approximation Method or remainder processing, that are operable to adjust values of reference trim bits used in trimming the bandgap reference. A tester system configured to perform testing of the integrated circuit may initiate execution of the test algorithm, thereby initiating the trimming process, and may wait for the test algorithm to complete within a previously defined amount of time, or may poll the logic circuitry to determine when the trimming process is complete.

Automatic reference voltage trimming technique

A temperature sensor circuit and system providing accurate readings using a temperature diode whose ideality factor may fall within a determined range. In one set of embodiments a change in diode junction voltage (&#x394;V) proportional to the temperature of the diode is captured and provided to an ADC, which may perform required signal conditioning functions on &#x394;V, and provide a numeric value output corresponding to the temperature of the diode. Errors in the measured temperature that might result from using diodes with ideality factors that differ from an expected ideality factor may be eliminated by programming the system to account for differing ideality factors. The gain of the temperature sensor may be matched to the ideality factor of the temperature diode by using an accurate, highly temperature stable reference voltage of the ADC to set the gain of the temperature measurement system. The reference voltage may have a trim capability to change the gain setting voltage by a digital address comprising a determined number of bits, with the programmable range for the reference voltage corresponding to a determined range of ideality factors.

Programmable ideality factor compensation in temperature sensors

An amplifier circuit. In one embodiment, the amplifier circuit includes an output stage and a gain stage. The gain stage includes first and second differential output terminals that may be coupled to first and second differential input terminals of the output stage. The gain stage includes a first feedback loop and a second feedback loop. First and second half-stages within the gain stage may be coupled to provide the second feedback loop. The first half-stage may be coupled to control a first output current at the first output terminal of the gain stage, while the second-half-stage may be coupled to control a second output current at the second output terminal of the gain stage.

Amplifier circuit with common mode feedback

A new safety glove for allowing a user, such as a police officer or a road worker, to direct traffic more easily. The inventive device includes a hand cover having an interior hand space, a front, a back, a palm portion, and a wrist opening into the interior hand space. Also provided are front and back reflective panels. The front reflective panel is coupled to the front of the hand cover and the back reflective panel is coupled to the back of the hand cover.

Safety glove

A circuit for producing a reference voltage includes an NPN transistor having its emitter connected to a first terminal, its collector connected to a second terminal, a PNP transistor having its emitter connected to the second terminal, its base connected to the base of the NPN transistor, and having its collector connected to the second terminal. A current source is connected to either the first terminal or the second terminal to force a current which is divided into a current through the PNP transistor and another current through the NPN transistor. The circuit produces a reference voltage equal to the sum of the PNP V.sub.BE voltage and the NPN V.sub.BE voltage. The reference voltage tracks precisely with variations in saturation currents of the PNP transistor and the NPN transistor. The circuit is useful in producing a two V.sub.BE bias voltage between the base of an NPN pullup transistor and a PNP pulldown transistor having a common emitter connection to an output terminal. The circuit produces a constant quiescent bias current in the NPN pullup transistor and the PNP pulldown transistor that is substantially independent of variations in the saturation currents of the PNP transistor and the NPN transistor.

Bias voltage generator and method

A 12 bit, 10 megahertz subranging analog-to-digital converter produces a sampled analog input signal. The sampled analog signal is converted by an MSB flash encoder to a 7 bit MSB word that is converted to an analog signal by a 7 bit DAC having 14 bit accuracy. The result is subtracted from the sample analog signal to produce a residue signal by means of a high speed amplifier having first and second multiplexed differential input stages, the first input stage having differential inputs receiving the sampled analog input signal and the analog signal produced by the 7 bit DAC. The second differential input stage has one input connected to ground and the other input resistively coupled to the output of the high speed amplifier. The output of the high speed amplifier is resistively coupled to the second input of the first and second differential stages. The multiplexed input high speed amplifier produces an intermediate input level until the output of the DAC is stable. Amplifying of the residue signal then begins from a balanced amplifier condition, and avoids delays that might result from an initial overdriven amplifier condition.

Subranging analog-to-digital converter with multiplexed input amplifier

A plurality of input stages having their outputs connected to provide differential currents to a load. When a bias current flows through a selected one of the input stages, the differential currents are provided in response to a differential signal provided to the selected stage. The input stages are each comprised of a pair of emitter-coupled transistors. Resistors are connected in series with the emitters of the transistors and the bias current is directly proportional to absolute temperature. The resistors may be adjusted to cause the offset voltages of the input stages to substantially equal zero at all temperatures.

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Tucson, AZ, United States of America

Thomas R Anderson