Panavision Imaging LLC

Thomas Poonnen

Jeffrey Jon Zarnowski

Ketan Vrajlal Karia

Michael Joyner

Li Liu

A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output with a level that varies corresponding to the contents of the counter. A latch/counter or equivalent is associated with each respective column. A clock supplies clock signal(s) to the counter elements. When the analog ramp equals the pixel value for that column, the latch/counter latches the value. The black level can be pre-set in the latch/counter or can be subtracted separately to reduce fixed pattern noise. The pixels can be oversampled for some number of times, e.g., n=16, to reduce the thermal noise of the sensors. Also, two or more pixels sharing a common sense node may be binned together, and two (or more) pixels having different integration times may be combined to obtain an output signal with enhanced dynamic range.

Image sensor ADC and CDS per column with oversampling

Improving the dynamic range of captured images is disclosed by using sub-pixel arrays to capture light at different exposures and generate color pixel outputs for an image in a single frame. Each sub-pixel array can include multiple sub-pixels. The sub-pixels that make up a sub-pixel array can include red (R) sub-pixels, green (G) sub-pixels, blue (B) sub-pixels, and in some embodiments, clear sub-pixels. Those sub-pixel arrays having clear sub-pixels effectively have a higher exposure level and can capture low-light scenes (for dark areas) better than those sub-pixel arrays without clear sub-pixels. Each sub-pixel array can produce a color pixel output that is a combination of the outputs of the sub-pixels in the sub-pixel array. Each sub-pixel in a sub-pixel array can have the same exposure time, or in some embodiments, individual sub-pixels within a sub-pixel array can have different exposure times to improve the overall dynamic range even more.

Sub-pixel array optical sensor

A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. A counter is coupled to an N-bit DAC to produce an analog ramp that varies corresponding to the contents of the counter. A ripple counter is associated with each respective column. A clock or a source of counts at a predetermined sequence supplies clock signals or counts to the counter elements. Column comparators gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a video output bus to produce the digital video signal. Additional black-level readout counters elements can create and store a black level digital value that is subtracted from the pixel value to reduce fixed pattern noise. The counters may employ two's complement arithmetic. An additional array of buffer counter/latches can be employed. Ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses or counts for the DAC counter and for the ripple counters can be at the same or different rates.

Image sensor ADC and CDS per column

A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk. An array of microlenses is situated with each microlens covering a plurality of the pixels. The different pixels under each microlens can be aligned along a diagonal. The different pixels under the same microlens can have different integration times, to increase the dynamic range of the imager(s).

Scanning imager employing multiple chips with staggered pixels

A solid state imager converts analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output with a level that varies corresponding to the contents of the counter. A ripple counter or equivalent is associated with each respective column. A clock supplies clock signals to the counter elements. A comparator in each column gates the counter element when the analog ramp equals the pixel value for that column. The contents of the counters are transferred sequentially to a video output bus to produce the digital video signal. Additional black-level readout counter elements can create and store a digital value that corresponds to a dark or black video level. A subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer counter/latches can be employed. The ripple counters can be configured as counters to capture the digital video level, and then as shift registers to clock out the video levels to an output bus. The clock pulses for the DAC counter and for the ripple counters can be at the same or different rates.

A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangement minimizes color cross talk.

A solid state imaging system has at least one CMOS imager with first and second series of pixels in which the pixels of one series are offset, i.e., staggered, in respect to the pixels of the other series. Multiple imagers can be arrayed end to end, with jumper wires connecting the pixel output conductors or each so that the pixels feed into a common output amplifier for each series, to minimize chip to chip offset voltages. The pixels may be diagonally offset from one another, and a color imager can be constructed in which color ribbon filters are arranged diagonally across the imaging area. This arrangment minimizes color cross talk.

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Cortland, NY, United States of America

Thomas Poonnen