Qualcomm Incorporated

Microsoft Technology Licensing, LLC

International Business Machines Corporation

Other

Arm Limited

Thomas Philip Speier

James Norris Dieffenderfer

Thomas Andrew Sartorius

Richard Gerard Hofmann

Bernard Charles Drerup

Rodney Wayne Smith

Michael Scott McIlvaine

Brian Stempel

Barry Joe Wolford

Jaya Prakash Subramaniam Ganasan

Eric Francis Robinson

Jaya Prakash Ganasan

Robert Douglas Clancy

Joseph Gerald McDonald

Gagan Gupta

Jordi Mola

Garrett M Drapala

Victor Roberts Augsburg

Paul Michael Steinmetz

Michael B Mitchell

Jason Lawrence Panavich

Praveen Karandikar

Ravi Rajagopalan

Madhavan Thirukkurungudi Venkataraman

Pritha Ghoshal

Niket Choudhary

William Robert Reohr

Abolade Gbadegesin

Jeffrey Todd Bridges

Michael W Morrow

David Scott Ray

Roberto Avanzi

Manish Garg

Kenneth Alan Dockser

Vikramjit Sethi

Kevin Neal Magill

Jason Stewart Wohlgemuth

Yusuf Cagatay Tekmen

David Tennyson Harper, Iii

Harb Abdulhamid

Darren Lasko

Clint Wayne Mumford

William James McAvoy

Patrick Eibl

Nikhil Narendradev Sharma

Artur Klauser

Michael Richard Ouellette

Harold Wade Cain, Iii

Joel Abraham Silberman

Anthony Correale, Jr

Thuong Quang Truong

Francois Ibrahim Atallah

Andreas Lars Sandberg

Matthew James Horsnell

Jeffrey Herbert Fischer

Michael Thomas Fragano

Gurushankar Rajamani

Daren Eugene Streett

Perry Willmann Remaklus, Jr

Michael ThaiThanh Phan

Jeffery Howard Oppold

Derek Chiou

Luke Yen

Eric Ola Harald Liljedahl

Melinda Joyce Brown

Samar Asbe

Pedro Miguel Teixeira

James Edward Sullivan, Jr

Robert L Goldiez

Randall John Pascarella

Neelesh Govindaraya Pai

Cody D Hartwig

Ketan Vitthal Patel

John Ingalls

Kshitiz Saxena

Anand Krishnamurthy

Daniel Stephen Geise

Harsh Thakker

Kevin Jaget

Sang Hoon Lee

Andrew Joseph Rushing

Leslie Mark Debruyne

Robin Alexander Emery

Viren Ramesh Patel

Paul Steinmetz

Spencer Williams

Soheil Ebadian

Henry Arthur Pellerin, Iii

Michael Scott Mcilvaine

Brian Michael Stempel

Joseph Gerald Mcdonald

Michael William Morrow

Iii Henry Arthur Pellerin

John Sumner Ingalls

Treating main memory as a collection of tagged cache lines for trace logging. A computer system allocates a plurality of memory blocks, and a corresponding plurality of tags, within a main memory. Each tag indicates whether data stored in a corresponding memory block has been captured by an execution trace. The computer system synchronizes these tags with tags in a memory cache and manages a traced status of the memory blocks. This can include one or more of (i) setting a tag to indicate a memory block has not been captured based on identifying a direct memory access operation, (ii) setting a tag based on whether a paged-in value of a memory block has been captured, (iii) setting a tag or memory categorization based whether a memory block has been initialized, or (iv) setting a tag or memory categorization based whether a memory block is mapped to a file.

Treating main memory as a collection of tagged cache lines for trace logging

In response to instruction decoding circuitry decoding a conditional write instruction, processing circuitry determines whether a predetermined condition is satisfied for a target cache line corresponding to a target address specified by the conditional write instruction. If the predetermined condition is satisfied for the target cache line, a write request is issued to update the target cache line. If the predetermined condition is not satisfied for the target cache line, a failure indication is returned. The processing circuitry selects, depending on whether the sequence of instructions specifies cache-line-retention hint information applicable to the conditional write instruction, whether to prevent a unique coherency state of the target cache line being relinquished by a local cache associated with the processing circuitry for a retention period following processing of the conditional write instruction. The unique coherency state comprises a coherency state in which the processing circuitry has exclusive right to update the target cache line.

Cache-line retention hint information for conditional write instruction

A method, apparatus, and system for storing memory encryption realm key IDs is disclosed. A method comprises accessing a memory ownership table with a physical address to determine a realm ID associated with the physical address, accessing a key ID association structure with the realm ID to determine a realm key IS associated with the realm ID, and initiating a memory transaction based on the realm key ID. Once retrieved, the realm key ID may be stored in a translation lookaside buffer.

Method, apparatus, and system for storing memory encryption realm key IDs

Efficiently replacing software breakpoint instructions in processor-based devices is disclosed. In this regard, in one exemplary embodiment, a processor-based device is provided. The processor-based device comprises a system memory and a processor. The processor comprises a breakpoint slip register (BSR) configured to store an instruction of a software process that was replaced in the system memory by a software breakpoint instruction, and further comprises a breakpoint slip enable (BSE) indicator. The processor is configured to, during execution of the software process, execute the software breakpoint instruction. The processor is further configured to, responsive to executing the software breakpoint instruction, transfer program control to a debugger. The processor is also configured to, upon program control returning from the debugger, determine that the BSE indicator is set. The processor is additionally configured to, responsive to determining that the BSE indicator is set, execute the instruction stored in the BSR.

Efficiently replacing software breakpoint instructions in processor-based devices

Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system

Tracking memory block access frequency in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that is configured to include an access count table for tracking accesses to memory blocks. The access count table is a packed table that comprises a plurality of access count values, each of which corresponds to a memory block of a plurality of memory blocks. Upon detecting a memory access operation (i.e., data-side operations such as memory load operations, memory store operations, atomic increment operations, set operations, and the like, or instruction-side operations such as code fetch operations) directed to a given memory block, the PE increments an access count value corresponding to the memory block. The access count value then can be accessed (e.g., by a process executing on the PE), and used to determine an access frequency for the memory block.

Tracking memory block access frequency in processor-based devices

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions

Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address. In some embodiments, any address translation errors encountered are raised to an appropriate exception level, and may be raised synchronously or asynchronously with respect to an operation performed when the speculative translation instruction is executed.

Performing speculative address translation in processor-based devices

Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Cache-based trace logging using tags in an upper-level cache

Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Combining load or store instructions

An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.

Method, apparatus, and system for memory bandwidth aware data prefetching

Exemplary reach-based explicit dataflow processors and related computer-readable media and methods. The reach-based explicit dataflow processors are configured to support execution of producer instructions encoded with explicit naming of consumer instructions intended to consume the values produced by the producer instructions. The reach-based explicit dataflow processors are configured to make available produced values as inputs to explicitly named consumer instructions as a result of processing producer instructions. The reach-based explicit dataflow processors support execution of a producer instruction that explicitly names a consumer instruction based on using the producer instruction as a relative reference point from the producer instruction. This reach-based explicit naming architecture does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions, and thus is not limited to explicit naming of consumer instructions only within the same instruction block of the producer instruction.

Reach-based explicit dataflow processors, and related computer-readable media and methods

Growing community of inventors

Holly Springs, NC, United States of America

Thomas Philip Speier