International Business Machines Corporation

Thomas Pflueger

Cedric Lichtenau

Peter Altevogt

Matthias Fertig

Thomas E Morf

Nikolaj Moll

Timothy Michael Skergan

James Stephen Fields, Jr

Kevin Franklin Reick

Scott Barnett Swaney

Paul Frank Lecocq

Jens Kuenzer

Brian Chan Monwai

Martin Padeffke

Rolf Bernhard Hilgendorf

Martin Recktenwald

Peter Anthony Sandon

Klaus J Getzlaff

Gero Dittmann

Andreea Anghel

Cédric Lichtenau

Ralph C Koester

Jan Van Lunteren

Markus Kaltenbach

Ulrich Mayer

Hans-Werner Tast

Tilman Gloekler

Jonas R Weiss

Tobias Gemmeke

Rolf Fritz

Thuyen Le

Ulrich Weiss

Hagen Schmidt

Cordt W Starke

Mathew I Ringler

Stefan Bonsels

Andreas Schmid

Eric M Schwarz

Philip George Emma

Vijayalakshmi Srinivasan

Steven Michael Douskey

Harry S Barowski

William Eric Hall

Alexander Erik Mericas

Mack Wayne Riley

Gregory Scott Still

Allan Mark Hartstein

Thomas R Puzak

Elaine Rivette Palmer

Gerard M Salem

Tim Niggemeier

Jochen Preiss

Johannes Koesters

Jay Gerald Heaslip

Rolf B Hilgendorf

Andreas Koenig

Friedrich Schroeder

Ingemar Holm

Antje Mueller

Florian Braun

Erwin B Cohen

Christoph Jaeschke

Miles G Canada

Dana J Thygesen

Edward Michael Seymour

Daniel Becker

Christian Mertin

Dedric Lichtenau

Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N&#x3e;2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.

Computerized branch predictions and decisions

A processor unit for processing storage instructions. The processor unit comprises a detection logic unit configured to identify at least two storage instructions for moving addressable words between registers of the processor unit and neighboring storage locations. The processor unit further comprises a combination unit configured to combine the identified instructions into a single combined instruction; and a data movement unit configured to move the words using the combined instruction.

Method and apparatus for processing storage instructions

A method for dynamically selecting a size of a memory access may be provided. The method comprises accessing blocks having a variable number of consecutive cache lines, maintaining a vector with entries of past utilizations for each block size, and adapting said block size before a next access to the blocks.

Selection of variable memory-access size

The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.

Enhanced performance-aware instruction scheduling

A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.

Performance-aware instruction scheduling

Secure extraction of state information of a computer system is provided. A method includes obtaining, by a security engine of a system, a public encryption key associated with a private decryption key; generating an extraction key that is inaccessible outside of the security engine; encrypting the extraction key with the public encryption key, to thereby obtain an encrypted extraction key; collecting state information of the system; encrypting the collected state information with the extraction key and storing the encrypted collected state information; and based on a request for access to the stored encrypted collected state information by a request for the extraction key, providing the extraction key to facilitate decryption of the stored encrypted state information.

Confidential extraction of system internal data

Secure initialization of the state of an electronic circuit. A processor determines the trusted state of one or more architecture state registers of an intellectual property core. The processor clears entries in a memory of the intellectual property core. The processor verifies that state machines, included in execution logic of the intellectual property core, have not generated output.

Verification of intellectual property core trusted state

The photo detector () comprises a photo transistor (). The photo transistor has a light sensitive region () for controlling the transistor action of the photo transistor. The photo detector further comprises a dielectric layer (). The dielectric layer is in contact with the photo transistor. The photo detector further comprises a grating pattern () in contact with the dielectric layer. The grating layer and the dielectric layer are adapted for focusing electromagnetic radiation in the light sensitive region.

Photo detector and integrated circuit

A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity.

Advanced Pstate structure with frequency computation

A method and apparatus for designing a device to operate in a coupling mode, a detection mode, or a reflection mode for incident light. The incident light has a wavelength &#x3bb; and is incident upon a semiconductor structure of the device at an angle of incidence (&#x3b8;). A voltage (V) is applied to the device. Each mode may be designed for an ON state and/or OFF state. For the coupling mode and detection mode, the ON state and OFF state is characterized by high and low absorption of the incident light, respectively, by the semiconductor structure in conjunction with the applied voltage V and angle of incidence &#x3b8;. For the reflection mode, the OFF state and ON states is characterized by a shift in the optical path length of &#x3bb;/2 and about zero, respectively, in conjunction with the applied voltage V and angle of incidence &#x3b8;.

Computer implemented design of device for electro-optical modulation of light incident upon device

The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module () via the voltage supply line. The supply voltage is composed of a reference voltage and a number of additional voltage levels. The reference voltage is defined by a voltage source and controlled by the integrated circuit via the bus, and the number of additional voltage levels is determined by the integrated circuit and send to the voltage regulation module via the sense line. Further the present invention relates to a corresponding apparatus with a voltage regulation module and an integrated circuit.

Method for controlling the supply voltage for an integrated circuit and an apparatus with a voltage regulation module and an integrated circuit

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Leinfelden, Germany

Thomas Pflueger