Infineon Technologies Ag

Qimonda Ag

Infineon Technologies LLC

Thomas Peter Haneder

Harald Bachhofer

Hans Reisinger

Reinhard J Stengl

Marcus Halik

Thomas Mikolajick

Till Schl&ouml;sser

Hagen Klauk

Christine Dehm

Wolfgang H&ouml;nlein

Günter Schmid

Georg Braun

Hermann Wendt

Wolfgang Hönlein

Josef Willer

Volker Lehmann

Walter Hartner

Franz Kreupl

Manfred Schneegans

Martin Franosch

Heinz Hoenigschmid

Richard Johannes Luyken

Gerhard Beitel

Wolfgang Hoenlein

Oswald Spindler

Gerrit Lange

Guenther Schindler

Rainer M Waser

Grit Sommer

Eugen Unger

Alfred Martin

Herbert Sch&auml;fer

Florian Binder

Stephan Dertinger

G&uuml;nter Schmid

Reinhard Marz

Holger Goebel

Marc Ullmann

Karin Fuchs

Michaela Fritz

Judith Lehmann

Stephan Schlamminger

Chip carrier with reduced interference signal sensitivity

Device having a flat macroporous support material made of silicon and having surfaces, a plurality of pores each having a diameter in a range of from 500 nm to 100 &#x3bc;m distributed over at least one surface region of the support material and extending from one surface through to the opposite surface of the support material, at least one region having one or more pores with SiO2 pore walls, and a frame of walls with a silicon core surrounding the at least one region and arranged essentially parallel to longitudinal axes of the pores and open towards the surfaces, wherein the silicon core merges into silicon dioxide over a cross section towards an outer side of the walls forming the frame.

Device based on partially oxidized porous silicon and method for its production

A semiconductor circuit configuration has at least one pair of complementary operating field-effect transistors in which each transistor has a gate region, first and second source/drain regions and also a channel region with or made of an organic semiconductor material that is provided in between. It is furthermore provided that the gate regions are formed such that they are electrically coupled to one another via a capacitor configuration.

Semiconductor circuit configuration and semiconductor memory device

The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode configuration and the insulation region, and in that the modulation region has or is formed from a material or modulation material having electrical and/or further material properties that can be modulated in a controllable manner between at least two states in such a way that, in accordance with these states of the modulation material or of the modulation region, the channel region can be influenced electromagnetically, in particular for a given electrical potential difference between the first gate electrode and the source/drain regions.

Semiconductor memory cell and semiconductor memory device

The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.

Method for reading out or in a status from or to a ferroelectrical transistor of a memory cell and memory matrix

The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor

In a method for producing ferroelectric strontium bismuth tantalate having the composition Sr Bi Ta O (SBT) or Sr Bi (Ta, Nb) O (SBTN), the element strontium, which is normally present in an amount y&equals;2, is provided in excess in a range from 2.1&lE;y&lE;3.0. This makes it possible to carry out the heat treatment step for converting the deposited material into the ferroelectric phase at a temperature T , which is lower than 700&deg; C. In addition, the strontium content x can be reduced from a nominal value of 1 to 0.7.

Low-temperature processing of a ferroelectric strontium bismuth tantalate layer, and fabrication of ferroelectric components using the layer

A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire being a semiconducting and/or metallically conductive nanowire. The field-effect transistor also has at least one nanotube, which forms a gate region of the field-effect transistor, the nanotube being a semiconducting and/or metallically conductive nanotube. The nanowire and the nanotube are arranged at a distance from one another or set up in such a manner that it is substantially impossible for there to be a tunneling current between the nanowire and the nanotube, and that the conductivity of the channel region of the nanowire can be controlled by means of a field effect as a result of an electric voltage being applied to the nanotube.

Field effect transistor

A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region that includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.

The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor substrate. The field effect transistor has a source area, a drain area, a channel area and a gate stack. The gate stack has at least one ferroelectric layer and at least one thin diffusion barrier layer being arranged between the lowest ferroelectric layer and the semiconductor substrate and being configured in such a way that an out-diffusion of the components of the ferroelectric layer into the semiconductor substrate is essentially prevented.

FEMFET device and method for producing same

A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric transistor

In a ferroelectric transistor containing two source/drain zones with a channel region disposed there-between, a first dielectric intermediate layer containing Al O is disposed on a surface of the channel region. A ferroelectric layer and a gate electrode are disposed above the first dielectric intermediate layer. The utilization of Al O in the first dielectric intermediate layer results in the suppression of tunneling of compensation charges from the channel region into the first dielectric layer and thereby improves the time for data storage.

Ferroelectric transistor

A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between source/drain regions at the surface of a semiconductor substrate. The first gate intermediate layer contains at least one ferroelectric layer. Beside the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are disposed between the source/drain regions, the second gate intermediate layer containing a dielectric layer. The first gate electrode and the second gate electrode are connected to one another through a diode structure. Strip-type doped well regions are provided in the semiconductor substrate, which well regions run between the source/drain regions of the respective ferroelectric transistor.

Ferroelectric memory cell with diode structure to protect the ferroelectric during read operations

A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

Ferroelectric transistor and memory cell configuration with the ferroelectric transistor

A DRAM capacitor is described that contains a BaSrTiO (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.

DRAM memory capacitor having three-layer dielectric, and method for its production

Growing community of inventors

Munich, Germany

Thomas Peter Haneder