Synopsys, Inc.

Arc International

Thomas Pennello

Peter R Warnes

Richard A Fuhler

Michael Lee Jalkut

Vineet Gupta

Tom Michiels

Henry A Davis

Disclosed herein are apparatus, method, and computer-readable storage device embodiments for implementing deconvolution via a set of convolutions. An embodiment includes a convolution processor that includes hardware implementing logic to perform at least one algorithm comprising a convolution algorithm. The at least one convolution processor may be further configured to perform operations including performing a first convolution and outputting a first deconvolution segment as a result of the performing the first convolution. The at least one convolution processor may be further configured to perform a second convolution and output a second deconvolution segment as a result of the performing the second convolution. According to some embodiments, the at least one convolution processor may be further configured to perform at least one further convolution to generate at least one further deconvolution segment, until a number of deconvolution segments output by the convolution processor reaches a deconvolution-size-value.

Deconvolution by convolutions

Techniques for mixed precision quantization of a machine learning (ML) model. A target bandwidth increase is received (), for the ML model () including objects of a first data type represented by a first number of bits. The target bandwidth increase relates to changing a first portion of the objects to a second data type represented by a second number of bits different from the first number of bits (). The method further includes sorting the objects in the ML model based on bandwidth (). The method further includes identifying the first portion of the objects to change from the first data type to the second data type, based on the target bandwidth increase and the sorting of the plurality of objects (). The method further includes changing the first portion of the objects from the first data type to the second data type ().

Mixed-precision neural networks

A system and a method are disclosed for more efficiently handling shared code stored in memory, comprising a modified memory management unit containing a new shared address space identifier register, and a modified TLB entry containing a new shared bit.

Extending processor MMU for shared address spaces

Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the 'regular' 32-bit instruction addressing modes, and the second for the 'compressed' 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.

Methods and apparatus for compiling instructions for a data processor

A method and apparatus for analyzing and formatting strings of data, such as data derived from software processes running on two data processors. In one embodiment, a plurality of different data strings are initialized building a symbol array, and finding differences within the data by analyzing various relationships within the data strings, such as the existence of unique strings. A computer program and apparatus for synthesizing logic implementing the aforementioned methodology are also disclosed.

Difference engine method and apparatus

A method and apparatus for debugging programs in a distributed environment, such as a set of heterogeneous hardware processors (integrated circuits or In-Circuit Emulators), and/or software-based simulators. In one embodiment, the method comprises identifying a plurality of processes; initializing each of the processes; executing with a single thread of control among the processes; and continuously cycling among the processes to obtain status information. A computer program and apparatus for implementing the aforementioned methodology are also disclosed.

Growing community of inventors

Santa Cruz, CA, United States of America

Thomas Pennello