Imec Vzw

Universidad Complutense De Madrid

Stitching Imec Nederland

Thomas Papastergiou

Francky Catthoor

Jose Ignacio Gomez

Matthias Hartmann

Christian Tenllado

Anup Kumar Das

Dimitrios Soudris

Sotiris Xydis

Javier Setoain Rodrigo

Christos Baloukas

The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

Memory structure comprising scratchpad memory

Growing community of inventors

Athens, Greece

Thomas Papastergiou