Sun Microsystems, Inc.

Thomas P Webber

Curtis R Priem

Hugh Kurth

Chris A Malachowsky

Paul Andrew Wilcox

Robert Dickson

Ketan P Joshi

Michael G Lavelle

Mark Donald Hill

Satyanarayana Nishtala

Glenn A Dearth

David Allen Wood

Daniel E Lenoski

Christopher J Jackson

Robert Zak

Monica C Wong-Chan

Peter A Mehring

Kenneth A Ward

Guy Moffat

Robert M Bauer

Christopher R Owen

Farroukh Touserkani

Ting-Chuck Chiang

An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send a response to the sending device to indicate that it is temporarily unavailable. The response can include a delay value that can provide a hint to the sending device as to when to resend the request. The target device may generate the delay value according to the type of condition that is causing it to be temporarily unavailable. The delay value may be generated according to a static heuristic or a dynamic algorithm based on previous temporarily unavailable conditions. The delay value may also be used by an error recovery mechanism where a sending device exceeds a retry limit for a particular request.

System and method for enhancing communication between devices in a computer system

Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer. The packet buffer may be divided into sections containing alternating lines of data to increase storage speed.

Method and system for buffering a data packet for transmission to a network

A method is provided for the precise reporting of errors in a flow of successive messages. The method includes detecting a transmission error in a message and then deferring the reporting of the transmission error. The method defers the reporting of the transmission error by saving a sequence number for the message and by setting a deferred error flag in a state saved for the flow. The method processes the deferred transmission error when it receives an acknowledgement that completes an immediately preceding message in the flow. When a positive acknowledgement is received, the deferred transmission error is reported. When a negative acknowledgement is received, the deferred transmission error is ignored and a remote error is reported.

Precise error reporting

During a scan operation in a circular, singly linked list having a number of list entries each of which has an associated next pointer field and a root pointer register that includes a root pointer that points to, or otherwise references, an arbitrary list entry. In order to add a new list entry to the list, the root pointer included in the root pointer register is copied into a next pointer field of the added list entry. Next, the root pointer register is overwritten with a pointer that points to or otherwise references the added list entry. In this way, additions to a circular, singly linked list that are done at the time of scanning involve only a single SRAM write access.

Additions on circular singly linked lists

A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively. By using a sideline buffer to temporarily store incomplete write instructions, processing of sequential memory access instructions can continue subject to observance of memory access conflict rules.

Split write data processing mechanism for memory controllers utilizing inactive periods during write data processing for other transactions

A system and method for reducing the number of memory accesses by a hardware device to a descriptor memory is disclosed. Methods, systems and articles of manufacture consistent with the present invention enable software to embed a subsequent descriptor it is posting in the descriptor memory into a current descriptor listed in the descriptor memory. Additionally, hardware is configured to transmit a data packet associated with the current descriptor to a recipient device. When hardware receives an acknowledgment message from the recipient device associated with the transmitted data packet, it fetches the current descriptor to update a completion code within the current descriptor using a Read-Modify-Write (RMW) transfer sequence. As part of the RMW memory operation, hardware may use the embedded copy of the subsequent descriptor within the current descriptor to transmit the next data packet associated with the subsequent descriptor. This process avoids hardware from having to fetch the embedded descriptor from the descriptor memory before transmitting the next data packet.

Methods, system and article of manufacture for pre-fetching descriptors

Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer.

System and method for building packets

A method for transmitting messages between two processes includes creating a communications channel between a first channel adapter coupled to a client process and a second channel adapter coupled to a remote process. The method further includes reading a request message at the first channel adapter, segmenting the request message into a series of packets, assigning a sequence number to each packet, and transmitting the packets in order to the second channel adapter through the communications channel. The method further includes receiving the packets at the second channel adapter and sending at least one acknowledgement message to the first channel adapter in response to the received packets. The acknowledgement message has a packet sequence number field containing a packet sequence number and a payload containing a message sequence number, wherein the message sequence number identifies a complete message last received at the second channel adapter and the packet sequence number identifies a packet last received at the second channel adapter.

Mechanism for completing messages in memory

Methods and apparatus for deleting a member in a circular singly linked list are described. Just prior to the current pointer register being updated, its contents are copied to the previous pointer register. When the consumer needs to delete a member from the list, the previous member location is known because it is saved in the previous pointer register. In this way, deletions done at the time of scanning involve only a single SRAM write access since the contents of the current pointer register is copied into the member referenced by the previous pointer register.

Deletions on circular singly linked lists

A network adapter includes a bypass buffer with sufficient capacity to store a packet from an upstream neighboring adapter and to store at least one additional incoming packet as a local packet is sent. The adapter also includes control logic which monitors the bypass buffer to determine whether the adapter may send local data packets. A network may be formed of such network adapters linked through counterrotating rings. If the control logic determines that the bypass buffer has sufficient storage available to avoid overflow while the adapter sends the local packet, the adapter sends the local packet. The control logic may choose to send a local packet only if there is sufficient room available within the bypass buffer to store a packet the same size as the local packet which is to be sent, thereby insuring that the bypass buffer does not overflow before the adapter can resume transmitting data from the bypass buffer. If there is not sufficient room within the adapter's bypass buffer, the adapter requests a pause in transmissions from its upstream neighbor which pause will permit the adapter to empty its bypass buffer and to then send a local packet. If the upstream neighbor cannot accommodate the pause request, it, in turn, requests a pause from its own upstream neighboring adapter, and so on, until a pause is effected and the original pause-requesting adapter can empty its bypass buffer and transmit its local packet.

Method and apparatus for providing a network interface

A buffer management subsystem receives data from one or more source processes for transfer to one or more destination processes. The buffer management subsystem includes a buffer memory and a buffer pointer FIFO that associated with one of the destination process. The buffer pointer FIFO stores pointers to buffers in the buffer memory which are available to be used to store data from the source process(es) for transfer to the respective associated destination process. When data is received from a source process for transfer to a destination process, a buffer pointer is retrieved from the buffer pointer FIFO associated with the destination process and used in storing the data in the buffer pointed to by the buffer pointer. When the data is retrieved from the buffer for transfer to the destination process, the buffer pointer to the buffer is returned to the buffer pointer FIFO.

Buffer management system having an output control configured to retrieve data in response to a retrieval request from a requesting one of a plurality of destinations

A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet. If no older data packet is a member of the same set of which the selected data packet is a member, the selected data packet can be dequeued from the turnstile FIFO without violated the sequential order of data packets of the ordered set to which the data packet belong. Conversely, if an older data packet is of the same ordered set, the selected data packet cannot be dequeued. A turnstile FIFO according to the present invention can be particularly useful in routing traffic within a crossbar between various devices.

Data structure and method for managing multiple ordered sets

A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes. This overlapping operation allows the bus to be completely utilized during write operations, thereby improving data bandwidth.

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Petersham, MA, United States of America

Thomas P Webber