National Semiconductor Corporation

Linear Technology Corporation

Thomas P Redfern

Joseph J Connolly, Jr

Thomas M Frederiksen

William C Rempfer

Thomas M Fredericksen

Comparators for use in a semi-flash analog-to-digital converter utilize switched capacitor inputs for effecting a subtraction of charge corresponding to the subtraction of voltages to obtain the most significant bit comparisons and least significant bit comparisons. In a preferred embodiment, a 6-input switched-capacitor comparator is employed in which an analog input signal, a most significant reference TAP, and the output from a digital-to-analog converter are sequentially coupled through a first capacitor to the input of an inverting amplifier. A second plurality of input terminals sequentially connects one-half the least significant bit reference potential, 0 volts, and a least significant reference voltage TAP through second capacitive means to the input of the inverting amplifier. One comparator can thereby perform both a most significant bit comparison and a least significant bit comparison in a semi-flash mode of operation.

Semi-flash A/D converter using switched capacitor comparators

A transceiver network having a driver and a receiver circuit for providing an interface between, for example, a data bus and a system controller or the like is disclosed herein. The receiver circuit includes a first logic gate of a first predefined type for providing output signals in response to input signals in accordance with a first transfer characteristic governed by a first reference voltage. A compensation arrangement is provided for adjusting the first reference voltage, and includes a first compensation gate of the first predefined type having an output governed by the first reference voltage. A first feedback loop coupled to the first compensation gate's output varies the first reference voltage until the first compensation gate generates a predefined output signal. The driver network includes a second input logic gate of a second predefined type having a first current transfer characteristic governed by a gate control voltage. A second compensation arrangement adjusts the gate control voltage, and includes a second compensation gate of the second predefined type having a current transfer characteristic proportional to the first current transfer characteristic. A second feedback loop coupled to the second compensation gate varies the gate control voltage until current flowing through the second compensation gate matches a supply current.

Method and apparatus for feedback control of I/O characteristics of

A bidirectional shift register includes a plurality of serially connected cells with each cell having a first circuit portion and a second circuit portion. Each circuit portion includes at least two parallel inverters connected in opposite directions. The relative transconductance of the oppositely connected inverters in each circuit portion of a cell can be varied thereby determining the direction of data flow through the circuit portion and through the bidirectional shift register.

Bidirectional shift register using parallel inverters with adjustable

Offsets in a chopper stabilized CMOS operational amplifier are nulled by adjusting the transconductance of the load transistors in the CMOS transistor pairs. This is accomplished by providing a small N channel transistor in parallel with each N channel load transistor of the CMOS pairs. A bias voltage is applied to the gate of one of the transistors and a voltage applied to the gate of the other N channel transistor. The voltage is developed by shorting the inputs to the operational amplifier and closing a feedback path around the input stage to null its offset. The nulling voltage taken at the gate of the other N channel transistor is capacitively stored and used during the subsequent sampling cycle.

Precision operational amplifier using data sampling

A single chip integrated circuit analog-to-digital converter uses the successive approximation approach with resistor ladder-switching decoder digital-to-analog coverters coupled to a precision plural input comparator. An on board PROM is provided to store in digital form the information necessary to trim the digital-to-analog converters. The converter is actuated during wafer probing in the manufacturing process and the PROM is programmed with the trim information. Initially, the PROM is bypassed and the digital words needed for accurate trim applied externally. Once the correct trim words are found, the PROM is programmed with the correct words. A 13-bit converter is supplied with ten 7-bit trim words to achieve a fully trimmed product in wafer fabrication.

Digital error correcting trimming in an analog to digital converter

A CMOS inverter is coupled to drive a bipolar transistor emitter follower which has a field effect transistor load. The load transistor is provided with a d-c bias that causes the circuit to function as a class A amplifier. The amplifier has a gain-band-width product that is much higher than can be achieved with CMOS inverters alone and such amplifiers can be cascaded to achieve extremely high gain values. It is preferred to obtain the required class A bias from a similar circuit wherein the load transistor is replaced by a resistor and the emitter follower has its output directly coupled to the CMOS inverter input. This means that the voltage across the resistor is that value that will operate the bias circuit at its trip point independent of the manufacturing variables that affect transistor threshold values. This amplifier configuration is useful in constructing high-speed, high-sensitivity clocked comparators and clocked latches.

Wide bandwidth CMOS class A amplifier

A read only memory is fabricated using metal oxide semiconductor technology and is intended for incorporation into large scale integrated circuits. A plurality of memory transistors is arrayed in a configuration having columns, each of which is associated with an address line, and rows, each of which is associated with a word line. A memory transistor is located at each intersection of an address line and a word line. Each memory transistor represents a bit location and includes a severable conductive link coupled in series and located on top of the field oxide surrounding the memory transistors. Each memory transistor in a particular column has its gate coupled to an address line. Each memory transistor in a particular row completes a series circuit which includes the severable conductive link between a first power supply terminal and a word line. Each word line includes a resistor coupled to the other power supply terminal. When a particular column is addressed, and the associated transistors in the address line turned on, all of the bits in the associated word will be 'ones.' The memory is programmed as desired after circuit manufacture in the wafer die sort operation by severing selected links with a laser beam. The severed device will program a 'zero' into the bit location. The word lines are coupled to a decoder that employs an array of gates having input pairs, one of which displays hysteresis. The memory also includes an external program simulation circuit which permits externally generating a particular digital word to simulate the memory content prior to programming.

Laser programmable read only memory

Two digital-to-analog converters are coupled in series across a reference potential source. Each converter includes a resistor ladder and switching tree that permits coupling the output to any single tap on the ladder. A digital word is split into two portions, each one of which operates one switching tree. The converters are weighted in accordance with the word bits applied. The switching tree outputs are combined to produce an analog output related to the reference potential and the digital word.

Double digital-to-analog converter

A high-gain, capacitor-coupled, chopper-stabilized, direct-current, voltage amplifier is capacitor coupled to a plurality of input switch pairs, each of which alternately couples one of a pair of input terminals to the amplifier. Thus, a voltage comparator results which has a plurality of pairs of inverting and non-inverting inputs. The relative contribution of the inputs can be weighted by ratioing the coupling capacitors of the switch pairs.

Precision plural input voltage amplifier and comparator

A capacitor suitable for integration into a monolithic integrated circuit is fabricated in two parallel connected sections. One section, using a thin oxide, constitutes most of the capacitance. A second section fabricated on a thick oxide constitutes a smaller capacitance per unit area but can be laser trimmed to provide a precise capacitance without damage to the integrated circuit. The trimmable section is desirably made using a conductive electrode material that is readily removed with laser energy.

Trim structure for integrated capacitors

A chopper stabilized comparator which compares two low level DC signals, and converts these signals to an AC signal which is amplified by AC amplifiers. The AC amplifier output is proportional to the difference between the two DC signals. The circuit has the advantage that it does not have any DC offset terms, for example, it does not drift with temperature. The comparator is implemented in CMOS technology wherein the actual physical layout of the circuit is chosen such that changes in mask orientation during the fabrication process have no effect upon the proper operation of the circuit.

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Thomas P Redfern